diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e02b893..924ab23 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1137,7 +1137,8 @@ endmenu menu "CPU Power Management" -if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA) +if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA || \ + ARCH_S3C64XX) source "drivers/cpufreq/Kconfig" @@ -1177,6 +1178,10 @@ config CPU_FREQ_PXA default y select CPU_FREQ_DEFAULT_GOV_USERSPACE +config CPU_FREQ_S3C + bool "CPUfreq support for Samsung CPUs" + depends on CPU_FREQ && CPU_S3C6410 + endif source "drivers/cpuidle/Kconfig" diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile index 8d7815d..5116579 100644 --- a/arch/arm/plat-s3c/Makefile +++ b/arch/arm/plat-s3c/Makefile @@ -30,3 +30,4 @@ obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o obj-y += dev-i2c0.o obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o +obj-$(CONFIG_CPU_FREQ_S3C) += cpufreq.o diff --git a/arch/arm/plat-s3c/cpufreq.c b/arch/arm/plat-s3c/cpufreq.c new file mode 100644 index 0000000..bc56ec5 --- /dev/null +++ b/arch/arm/plat-s3c/cpufreq.c @@ -0,0 +1,263 @@ +/* linux/arch/arm/plat-s3c/cpufreq.c + * + * Copyright 2009 Wolfson Microelectronics plc + * + * S3C CPUfreq Support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +static struct clk *armclk; +static struct regulator *vddarm; + + +#ifdef CONFIG_CPU_S3C6410 +struct s3c_dvfs { + unsigned int vddarm_min; + unsigned int vddarm_max; +}; + +static struct s3c_dvfs s3c_dvfs_table[] = { + [0] = { 1000000, 1000000 }, + [1] = { 1000000, 1050000 }, + [2] = { 1050000, 1100000 }, + [3] = { 1050000, 1150000 }, + [4] = { 1250000, 1350000 }, +}; + +static struct cpufreq_frequency_table s3c_freq_table[] = { + { 0, 66000 }, + { 0, 133000 }, + { 1, 222000 }, + { 1, 266000 }, + { 2, 333000 }, + { 2, 400000 }, + { 3, 532000 }, + { 3, 533000 }, + { 4, 667000 }, + { 0, CPUFREQ_TABLE_END }, +}; +#endif + +static int s3c_cpufreq_verify_speed(struct cpufreq_policy *policy) +{ + if (policy->cpu != 0) + return -EINVAL; + + return cpufreq_frequency_table_verify(policy, s3c_freq_table); +} + +static unsigned int s3c_cpufreq_get_speed(unsigned int cpu) +{ + if (cpu != 0) + return 0; + + return clk_get_rate(armclk) / 1000; +} + +static int s3c_cpufreq_set_target(struct cpufreq_policy *policy, + unsigned int target_freq, + unsigned int relation) +{ + int ret; + unsigned int i; + struct cpufreq_freqs freqs; + struct s3c_dvfs *dvfs; + + ret = cpufreq_frequency_table_target(policy, s3c_freq_table, + target_freq, relation, &i); + if (ret != 0) + return ret; + + freqs.cpu = 0; + freqs.old = clk_get_rate(armclk) / 1000; + freqs.new = s3c_freq_table[i].frequency; + freqs.flags = 0; + dvfs = &s3c_dvfs_table[s3c_freq_table[i].index]; + + if (freqs.old == freqs.new) + return 0; + + pr_debug("cpufreq: Transition %d-%dkHz\n", freqs.old, freqs.new); + + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + +#ifdef CONFIG_REGULATOR + if (vddarm && freqs.new > freqs.old) { + ret = regulator_set_voltage(vddarm, + dvfs->vddarm_min, + dvfs->vddarm_max); + if (ret != 0) { + pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n", + freqs.new, ret); + goto err; + } + } +#endif + + ret = clk_set_rate(armclk, freqs.new * 1000); + if (ret < 0) { + pr_err("cpufreq: Failed to set rate %dkHz: %d\n", + freqs.new, ret); + goto err; + } + +#ifdef CONFIG_REGULATOR + if (vddarm && freqs.new < freqs.old) { + ret = regulator_set_voltage(vddarm, + dvfs->vddarm_min, + dvfs->vddarm_max); + if (ret != 0) { + pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n", + freqs.new, ret); + goto err_clk; + } + } +#endif + + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + + pr_debug("cpufreq: Set actual frequency %lukHz\n", + clk_get_rate(armclk) / 1000); + + return 0; + +err_clk: + if (clk_set_rate(armclk, freqs.old * 1000) < 0) + pr_err("Failed to restore original clock rate\n"); +err: + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + + return ret; +} + +#ifdef CONFIG_REGULATOR +static void __init s3c_cpufreq_constrain_voltages(void) +{ + int count, v, i, found; + struct cpufreq_frequency_table *freq; + struct s3c_dvfs *dvfs; + + count = regulator_count_voltages(vddarm); + if (count < 0) { + pr_err("cpufreq: Unable to check supported voltages\n"); + return; + } + + freq = s3c_freq_table; + while (freq->frequency != CPUFREQ_TABLE_END) { + if (freq->frequency == CPUFREQ_ENTRY_INVALID) + continue; + + dvfs = &s3c_dvfs_table[freq->index]; + found = 0; + + for (i = 0; i < count; i++) { + v = regulator_list_voltage(vddarm, i); + if (v >= dvfs->vddarm_min && v <= dvfs->vddarm_max) + found = 1; + } + + if (!found) { + pr_debug("cpufreq: %dkHz unsupported by regulator\n", + freq->frequency); + freq->frequency = CPUFREQ_ENTRY_INVALID; + } + + freq++; + } +} +#endif + +static int __init s3c_cpufreq_driver_init(struct cpufreq_policy *policy) +{ + int ret; + struct cpufreq_frequency_table *freq; + + if (policy->cpu != 0) + return -EINVAL; + + if (s3c_freq_table == NULL) { + pr_err("cpufreq: No frequency information for this CPU\n"); + return -ENODEV; + } + + armclk = clk_get(NULL, "armclk"); + if (IS_ERR(armclk)) { + pr_err("cpufreq: Unable to obtain ARMCLK: %ld\n", + PTR_ERR(armclk)); + return PTR_ERR(armclk); + } + +#ifdef CONFIG_REGULATOR + vddarm = regulator_get(NULL, "vddarm"); + if (IS_ERR(vddarm)) { + ret = PTR_ERR(vddarm); + pr_err("cpufreq: Failed to obtain VDDARM: %d\n", ret); + pr_err("cpufreq: Only frequency scaling available\n"); + vddarm = NULL; + } else { + s3c_cpufreq_constrain_voltages(); + } +#endif + + freq = s3c_freq_table; + while (freq->frequency != CPUFREQ_TABLE_END) { + unsigned long r; + + /* Check for frequencies we can generate */ + r = clk_round_rate(armclk, freq->frequency * 1000); + r /= 1000; + if (r != freq->frequency) + freq->frequency = CPUFREQ_ENTRY_INVALID; + + /* If we have no regulator then assume startup + * frequency is the maximum we can support. */ + if (!vddarm && freq->frequency > s3c_cpufreq_get_speed(0)) + freq->frequency = CPUFREQ_ENTRY_INVALID; + + freq++; + } + + policy->cur = clk_get_rate(armclk) / 1000; + + /* Pick a conservative guess in ns: we'll need ~1 I2C/SPI + * write plus clock reprogramming. */ + policy->cpuinfo.transition_latency = 2 * 1000 * 1000; + + ret = cpufreq_frequency_table_cpuinfo(policy, s3c_freq_table); + if (ret != 0) { + pr_err("cpufreq: Failed to configure frequency table: %d\n", + ret); + regulator_put(vddarm); + clk_put(armclk); + } + + return ret; +} + +static struct cpufreq_driver s3c_cpufreq_driver = { + .owner = THIS_MODULE, + .flags = 0, + .verify = s3c_cpufreq_verify_speed, + .target = s3c_cpufreq_set_target, + .get = s3c_cpufreq_get_speed, + .init = s3c_cpufreq_driver_init, + .name = "s3c", +}; + +static int __init s3c_cpufreq_init(void) +{ + return cpufreq_register_driver(&s3c_cpufreq_driver); +} +module_init(s3c_cpufreq_init); diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c index 05b1752..e05ed02 100644 --- a/arch/arm/plat-s3c64xx/s3c6400-clock.c +++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c @@ -88,6 +88,76 @@ static struct clksrc_clk clk_mout_apll = { .sources = &clk_src_apll, }; +#ifdef CONFIG_CPU_S3C6400 +#define CLKDIV0_ARM_MASK S3C6400_CLKDIV0_ARM_MASK +#endif +#ifdef CONFIG_CPU_S3C6410 +#define CLKDIV0_ARM_MASK S3C6410_CLKDIV0_ARM_MASK +#endif + +static unsigned long s3c64xx_clk_arm_get_rate(struct clk *clk) +{ + unsigned long rate = clk_get_rate(clk->parent); + u32 val; + + val = __raw_readl(S3C_CLK_DIV0); + val &= CLKDIV0_ARM_MASK; + + return rate / (val + 1); +} + +static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk, + unsigned long rate) +{ + unsigned long parent = clk_get_rate(clk->parent); + int div; + int max = CLKDIV0_ARM_MASK + 1; + + if (parent < rate) + return parent; + + div = parent / rate; + + if (div < 1) + div = 1; + if (div > max) + div = max; + + return parent / div; +} + +static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int div; + u32 val; + unsigned long flags; + + div = (clk_get_rate(clk->parent) / rate) - 1; + + if (div > CLKDIV0_ARM_MASK) + return -EINVAL; + + local_irq_save(flags); + + val = __raw_readl(S3C_CLK_DIV0); + val &= ~CLKDIV0_ARM_MASK; + val |= div; + + __raw_writel(val, S3C_CLK_DIV0); + local_irq_restore(flags); + + return 0; +} + +static struct clk clk_arm = { + .name = "armclk", + .id = -1, + .parent = &clk_mout_apll.clk, + .round_rate = &s3c64xx_clk_arm_round_rate, + .get_rate = s3c64xx_clk_arm_get_rate, + .set_rate = s3c64xx_clk_arm_set_rate, +}; + static struct clk clk_fout_epll = { .name = "fout_epll", .id = -1, @@ -635,6 +705,7 @@ static struct clk *clks[] __initdata = { &clk_audio0.clk, &clk_audio1.clk, &clk_irda.clk, + &clk_arm, }; void __init s3c6400_register_clocks(void)