diff --git a/Documentation/sound/alsa/soc/dapm.txt b/Documentation/sound/alsa/soc/dapm.txt index 46f9684..9e67632 100644 --- a/Documentation/sound/alsa/soc/dapm.txt +++ b/Documentation/sound/alsa/soc/dapm.txt @@ -116,6 +116,9 @@ SOC_DAPM_SINGLE("HiFi Playback Switch", WM8731_APANA, 4, 1, 0), SND_SOC_DAPM_MIXER("Output Mixer", WM8731_PWR, 4, 1, wm8731_output_mixer_controls, ARRAY_SIZE(wm8731_output_mixer_controls)), +If you dont want the mixer elements prefixed with the name of the mixer widget, +you can use SND_SOC_DAPM_MIXER_NAMED_CTL instead. the parameters are the same +as for SND_SOC_DAPM_MIXER. 2.3 Platform/Machine domain Widgets ----------------------------------- diff --git a/Makefile b/Makefile index 681c1d2..22d7584 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ VERSION = 2 PATCHLEVEL = 6 SUBLEVEL = 29 -EXTRAVERSION = -rc4 +EXTRAVERSION = -rc5 NAME = Erotic Pickled Herring # *DOCUMENTATION* diff --git a/arch/arm/mach-pxa/e750.c b/arch/arm/mach-pxa/e750.c index be1ab8e..665066f 100644 --- a/arch/arm/mach-pxa/e750.c +++ b/arch/arm/mach-pxa/e750.c @@ -133,6 +133,11 @@ static unsigned long e750_pin_config[] __initdata = { /* IrDA */ GPIO38_GPIO | MFP_LPM_DRIVE_HIGH, + /* Audio power control */ + GPIO4_GPIO, /* Headphone amp power */ + GPIO7_GPIO, /* Speaker amp power */ + GPIO37_GPIO, /* Headphone detect */ + /* PC Card */ GPIO8_GPIO, /* CD0 */ GPIO44_GPIO, /* CD1 */ diff --git a/arch/arm/mach-pxa/include/mach/eseries-gpio.h b/arch/arm/mach-pxa/include/mach/eseries-gpio.h index efbd2aa..6d6e4d8 100644 --- a/arch/arm/mach-pxa/include/mach/eseries-gpio.h +++ b/arch/arm/mach-pxa/include/mach/eseries-gpio.h @@ -45,6 +45,16 @@ /* e7xx IrDA power control */ #define GPIO_E7XX_IR_OFF 38 +/* e750 audio control GPIOs */ +#define GPIO_E750_HP_AMP_OFF 4 +#define GPIO_E750_SPK_AMP_OFF 7 +#define GPIO_E750_HP_DETECT 37 + +/* e800 audio control GPIOs */ +#define GPIO_E800_HP_DETECT 81 +#define GPIO_E800_HP_AMP_OFF 82 +#define GPIO_E800_SPK_AMP_ON 83 + /* ASIC related GPIOs */ #define GPIO_ESERIES_TMIO_IRQ 5 #define GPIO_ESERIES_TMIO_PCLR 19 diff --git a/include/linux/mfd/wm8350/audio.h b/include/linux/mfd/wm8350/audio.h index af95a1d..d899dc0 100644 --- a/include/linux/mfd/wm8350/audio.h +++ b/include/linux/mfd/wm8350/audio.h @@ -490,6 +490,7 @@ /* * R231 (0xE7) - Jack Status */ +#define WM8350_JACK_L_LVL 0x0800 #define WM8350_JACK_R_LVL 0x0400 /* diff --git a/include/sound/soc-dapm.h b/include/sound/soc-dapm.h index dfa8049..bb3a863 100644 --- a/include/sound/soc-dapm.h +++ b/include/sound/soc-dapm.h @@ -76,6 +76,11 @@ wcontrols, wncontrols)\ { .id = snd_soc_dapm_mixer, .name = wname, .reg = wreg, .shift = wshift, \ .invert = winvert, .kcontrols = wcontrols, .num_kcontrols = wncontrols} +#define SND_SOC_DAPM_MIXER_NAMED_CTL(wname, wreg, wshift, winvert, \ + wcontrols, wncontrols)\ +{ .id = snd_soc_dapm_mixer_named_ctl, .name = wname, .reg = wreg, \ + .shift = wshift, .invert = winvert, .kcontrols = wcontrols, \ + .num_kcontrols = wncontrols} #define SND_SOC_DAPM_MICBIAS(wname, wreg, wshift, winvert) \ { .id = snd_soc_dapm_micbias, .name = wname, .reg = wreg, .shift = wshift, \ .invert = winvert, .kcontrols = NULL, .num_kcontrols = 0} @@ -101,6 +106,11 @@ { .id = snd_soc_dapm_mixer, .name = wname, .reg = wreg, .shift = wshift, \ .invert = winvert, .kcontrols = wcontrols, .num_kcontrols = wncontrols, \ .event = wevent, .event_flags = wflags} +#define SND_SOC_DAPM_MIXER_NAMED_CTL_E(wname, wreg, wshift, winvert, \ + wcontrols, wncontrols, wevent, wflags) \ +{ .id = snd_soc_dapm_mixer, .name = wname, .reg = wreg, .shift = wshift, \ + .invert = winvert, .kcontrols = wcontrols, \ + .num_kcontrols = wncontrols, .event = wevent, .event_flags = wflags} #define SND_SOC_DAPM_MICBIAS_E(wname, wreg, wshift, winvert, wevent, wflags) \ { .id = snd_soc_dapm_micbias, .name = wname, .reg = wreg, .shift = wshift, \ .invert = winvert, .kcontrols = NULL, .num_kcontrols = 0, \ @@ -250,10 +260,10 @@ int snd_soc_dapm_set_bias_level(struct snd_soc_device *socdev, int snd_soc_dapm_sys_add(struct device *dev); /* dapm audio pin control and status */ -int snd_soc_dapm_enable_pin(struct snd_soc_codec *codec, char *pin); -int snd_soc_dapm_disable_pin(struct snd_soc_codec *codec, char *pin); -int snd_soc_dapm_nc_pin(struct snd_soc_codec *codec, char *pin); -int snd_soc_dapm_get_pin_status(struct snd_soc_codec *codec, char *pin); +int snd_soc_dapm_enable_pin(struct snd_soc_codec *codec, const char *pin); +int snd_soc_dapm_disable_pin(struct snd_soc_codec *codec, const char *pin); +int snd_soc_dapm_nc_pin(struct snd_soc_codec *codec, const char *pin); +int snd_soc_dapm_get_pin_status(struct snd_soc_codec *codec, const char *pin); int snd_soc_dapm_sync(struct snd_soc_codec *codec); /* dapm widget types */ @@ -263,6 +273,7 @@ enum snd_soc_dapm_type { snd_soc_dapm_mux, /* selects 1 analog signal from many inputs */ snd_soc_dapm_value_mux, /* selects 1 analog signal from many inputs */ snd_soc_dapm_mixer, /* mixes several analog signals together */ + snd_soc_dapm_mixer_named_ctl, /* mixer with named controls */ snd_soc_dapm_pga, /* programmable gain/attenuation (volume) */ snd_soc_dapm_adc, /* analog to digital converter */ snd_soc_dapm_dac, /* digital to analog converter */ diff --git a/include/sound/soc.h b/include/sound/soc.h index 24593ac..7039343 100644 --- a/include/sound/soc.h +++ b/include/sound/soc.h @@ -154,6 +154,8 @@ enum snd_soc_bias_level { SND_SOC_BIAS_OFF, }; +struct snd_jack; +struct snd_soc_card; struct snd_soc_device; struct snd_soc_pcm_stream; struct snd_soc_ops; @@ -164,6 +166,8 @@ struct snd_soc_platform; struct snd_soc_codec; struct soc_enum; struct snd_soc_ac97_ops; +struct snd_soc_jack; +struct snd_soc_jack_pin; typedef int (*hw_write_t)(void *,const char* ,int); typedef int (*hw_read_t)(void *,char* ,int); @@ -184,6 +188,13 @@ int snd_soc_init_card(struct snd_soc_device *socdev); int snd_soc_set_runtime_hwparams(struct snd_pcm_substream *substream, const struct snd_pcm_hardware *hw); +/* Jack reporting */ +int snd_soc_jack_new(struct snd_soc_card *card, const char *id, int type, + struct snd_soc_jack *jack); +void snd_soc_jack_report(struct snd_soc_jack *jack, int status, int mask); +int snd_soc_jack_add_pins(struct snd_soc_jack *jack, int count, + struct snd_soc_jack_pin *pins); + /* codec IO */ #define snd_soc_read(codec, reg) codec->read(codec, reg) #define snd_soc_write(codec, reg, value) codec->write(codec, reg, value) @@ -203,6 +214,8 @@ void snd_soc_free_ac97_codec(struct snd_soc_codec *codec); */ struct snd_kcontrol *snd_soc_cnew(const struct snd_kcontrol_new *_template, void *data, char *long_name); +int snd_soc_add_controls(struct snd_soc_codec *codec, + const struct snd_kcontrol_new *controls, int num_controls); int snd_soc_info_enum_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo); int snd_soc_info_enum_ext(struct snd_kcontrol *kcontrol, @@ -237,6 +250,27 @@ int snd_soc_get_volsw_s8(struct snd_kcontrol *kcontrol, int snd_soc_put_volsw_s8(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); +/** + * struct snd_soc_jack_pin - Describes a pin to update based on jack detection + * + * @pin: name of the pin to update + * @mask: bits to check for in reported jack status + * @invert: if non-zero then pin is enabled when status is not reported + */ +struct snd_soc_jack_pin { + struct list_head list; + const char *pin; + int mask; + bool invert; +}; + +struct snd_soc_jack { + struct snd_jack *jack; + struct snd_soc_card *card; + struct list_head pins; + int status; +}; + /* SoC PCM stream information */ struct snd_soc_pcm_stream { char *stream_name; diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig index ef025c6..a04890f 100644 --- a/sound/soc/Kconfig +++ b/sound/soc/Kconfig @@ -6,6 +6,7 @@ menuconfig SND_SOC tristate "ALSA for SoC audio support" select SND_PCM select AC97_BUS if SND_SOC_AC97_BUS + select SND_JACK if INPUT=y || INPUT=SND ---help--- If you want ASoC support, you should say Y here and also to the @@ -28,6 +29,7 @@ source "sound/soc/au1x/Kconfig" source "sound/soc/blackfin/Kconfig" source "sound/soc/davinci/Kconfig" source "sound/soc/fsl/Kconfig" +source "sound/soc/imx/Kconfig" source "sound/soc/omap/Kconfig" source "sound/soc/pxa/Kconfig" source "sound/soc/s3c24xx/Kconfig" diff --git a/sound/soc/Makefile b/sound/soc/Makefile index 86a9b1f..a9ddea3 100644 --- a/sound/soc/Makefile +++ b/sound/soc/Makefile @@ -1,4 +1,4 @@ -snd-soc-core-objs := soc-core.o soc-dapm.o +snd-soc-core-objs := soc-core.o soc-dapm.o soc-jack.o obj-$(CONFIG_SND_SOC) += snd-soc-core.o obj-$(CONFIG_SND_SOC) += codecs/ @@ -7,6 +7,7 @@ obj-$(CONFIG_SND_SOC) += au1x/ obj-$(CONFIG_SND_SOC) += blackfin/ obj-$(CONFIG_SND_SOC) += davinci/ obj-$(CONFIG_SND_SOC) += fsl/ +obj-$(CONFIG_SND_SOC) += imx/ obj-$(CONFIG_SND_SOC) += omap/ obj-$(CONFIG_SND_SOC) += pxa/ obj-$(CONFIG_SND_SOC) += s3c24xx/ diff --git a/sound/soc/au1x/Kconfig b/sound/soc/au1x/Kconfig index 410a893..bfd0cb9 100644 --- a/sound/soc/au1x/Kconfig +++ b/sound/soc/au1x/Kconfig @@ -18,10 +18,10 @@ config SND_SOC_AU1XPSC_AC97 select SND_AC97_CODEC select SND_SOC_AC97_BUS - ## ## Boards ## + config SND_SOC_SAMPLE_PSC_AC97 tristate "Sample Au12x0/Au1550 PSC AC97 sound machine" depends on SND_SOC_AU1XPSC @@ -30,3 +30,21 @@ config SND_SOC_SAMPLE_PSC_AC97 help This is a sample AC97 sound machine for use in Au12x0/Au1550 based systems which have audio on PSC1 (e.g. Db1200 demoboard). + + +config SND_SOC_EXM1200_AC97 + tristate "MSC EXM32-Au1200 AC97 support" + depends on SND_SOC_AU1XPSC + select SND_SOC_AU1XPSC_AC97 + select SND_SOC_AC97_CODEC + help + AC97 sound support for EXM32 Development Motherboard + +config SND_SOC_EXM1200_SSI + tristate "MSC EXM32-Au1200 I2S support" + depends on SND_SOC_AU1XPSC + depends on I2C!=n + select SND_SOC_AU1XPSC_I2S + select SND_SOC_CS4251X + help + I2S sound support for EXM32 Development Motherboard diff --git a/sound/soc/au1x/Makefile b/sound/soc/au1x/Makefile index 6c6950b..b992c99 100644 --- a/sound/soc/au1x/Makefile +++ b/sound/soc/au1x/Makefile @@ -9,5 +9,9 @@ obj-$(CONFIG_SND_SOC_AU1XPSC_AC97) += snd-soc-au1xpsc-ac97.o # Boards snd-soc-sample-ac97-objs := sample-ac97.o +snd-soc-exmmb-ac97-objs := exmmb-ac97.o +snd-soc-exmmb-i2s-objs := exmmb-i2s.o +obj-$(CONFIG_SND_SOC_EXM1200_AC97) += snd-soc-exmmb-ac97.o +obj-$(CONFIG_SND_SOC_EXM1200_SSI) += snd-soc-exmmb-i2s.o obj-$(CONFIG_SND_SOC_SAMPLE_PSC_AC97) += snd-soc-sample-ac97.o diff --git a/sound/soc/au1x/dbdma.c b/sound/soc/au1x/dbdma.c new file mode 100644 index 0000000..88fb475 --- /dev/null +++ b/sound/soc/au1x/dbdma.c @@ -0,0 +1,417 @@ +/* + * dbdma - DBDMA for Au1200/Au1550 PSC Audio interfaces (AC97/I2S) + * + * Copyright (c) 2007 MSC Vertriebsges.m.b.H, + * + * licensed under the GPLv2. + * + */ + +/* + * TODO: the au1200/au1550 DBDMA API needs an overhaul or least a few + * extensions: + * - change STS/DTS (access size) for a descriptor ring on the fly: + * au1xxx_dbdma_adjust_size(chanid, int sts, int dts); + * - maybe even a way to add/remove descriptor from the ring, to support + * varying number of periods. + * - destroy/free a ring (certainly required for the above) + * - probably more I haven't thought about yet + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "psc.h" + +/*#define PCM_DEBUG*/ + +#ifdef PCM_DEBUG +#define MSG(x...) printk(KERN_INFO "au1x-pcm: " x) +#else +#define MSG(x...) do {} while (0) +#endif + +struct au1xpsc_pcm_dmadata { + struct snd_pcm_substream *substream; + unsigned long pos; /* current byte position being played */ + unsigned long periods; /* number of SG segments in total */ + unsigned long curr_period; /* current segment DDMA is working on */ + unsigned long period_bytes; /* size in bytes of one SG segment */ +}; + +static struct au1xpsc_pcm { + unsigned long pscbase; + unsigned int dmatx; + unsigned int dmarx; + + u32 tx_chan; + u32 rx_chan; + struct au1xpsc_pcm_dmadata dma_play; + struct au1xpsc_pcm_dmadata dma_rec; +} au1xpsc_pcm_data[PSC_COUNT] = { + { + .pscbase = PSC0_BASE, + .dmatx = DSCR_CMD0_PSC0_TX, + .dmarx = DSCR_CMD0_PSC0_RX, + }, + { + .pscbase = PSC1_BASE, + .dmatx = DSCR_CMD0_PSC1_TX, + .dmarx = DSCR_CMD0_PSC1_RX, + }, +#ifdef CONFIG_SOC_AU1550 + { + .pscbase = PSC2_BASE, + .dmatx = DSCR_CMD0_PSC2_TX, + .dmarx = DSCR_CMD0_PSC2_RX, + }, + { + .pscbase = PSC3_BASE, + .dmatx = DSCR_CMD0_PSC3_TX, + .dmarx = DSCR_CMD0_PSC3_RX, + }, +#endif +}; + + +/* + * These settings are somewhat okay, at least on my machine audio plays almost + * skip-free. Especially the 64kB buffer seems to help a LOT. + */ +#define AU1XPSC_PERIOD_MIN_BYTES 1024 +#define AU1XPSC_BUFFER_MIN_BYTES 65536 +#define AU1XPSC_PERIODS_MIN 4 + +/* PCM hardware DMA capabilities - platform specific */ +static const struct snd_pcm_hardware au1xpsc_pcm_hardware = { + .info = SNDRV_PCM_INFO_MMAP | + SNDRV_PCM_INFO_MMAP_VALID | + SNDRV_PCM_INFO_INTERLEAVED, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + /* later also S24 would be possible + SNDRV_PCM_FMTBIT_S24_LE, */ + .period_bytes_min = AU1XPSC_PERIOD_MIN_BYTES, + .period_bytes_max = 4096 * 1024 - 1, + .periods_min = AU1XPSC_PERIODS_MIN, + .periods_max = AU1XPSC_PERIODS_MIN, + .buffer_bytes_max = 4096 * 1024 - 1, + .fifo_size = 16, /* fifo entries of AC97/I2S PSC */ +}; + +/* one descriptor completed, update dma data */ +static inline void dma_update(struct au1xpsc_pcm_dmadata *dd) +{ + dd->curr_period++; + if (dd->curr_period >= dd->periods) { + /* if the NOCV flag is set, DBDMA should start with the + first descriptor again. Wrap around here too */ + dd->pos = 0; + dd->curr_period = 0; + } else + dd->pos += dd->period_bytes; +} + +static void au1x_dbdma_tx_callback(int irq, void *dev_id) +{ + struct au1xpsc_pcm *psc = dev_id; + dma_update(&psc->dma_play); + snd_pcm_period_elapsed(psc->dma_play.substream); +} + +static void au1x_dbdma_rx_callback(int irq, void *dev_id) +{ + struct au1xpsc_pcm *psc = dev_id; + dma_update(&psc->dma_rec); + snd_pcm_period_elapsed(psc->dma_rec.substream); +} + +/* + * Called by ALSA when the hardware params are set by application. This + * function can also be called multiple times and can allocate buffers + * (using snd_pcm_lib_* ). It's non-atomic. + */ +static int au1xpsc_pcm_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct au1xpsc_pcm *psc = &au1xpsc_pcm_data[rtd->dai->cpu_dai->id]; + struct au1xpsc_pcm_dmadata *dd; + int dir, len, segs, i, ret; + + MSG("pcm_hw_params() enter\n"); + + ret = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params)); + if (ret < 0) + goto out; + + dir = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1; + segs = params_periods(params); + len = params_period_bytes(params); + + dd = (dir) ? &psc->dma_rec : &psc->dma_play; + + /* invalidate whole DBDMA ring */ + au1xxx_dbdma_stop(dir ? psc->rx_chan : psc->tx_chan); + au1xxx_dbdma_reset(dir ? psc->rx_chan : psc->tx_chan); + + MSG("runtime->dma_area = 0x%08lx dma_addr_t = 0x%08lx dma_size = %d\n", + (unsigned long)runtime->dma_area, + (unsigned long)runtime->dma_addr, runtime->dma_bytes); + + for (i = 0; i < segs; i++) { + if (dir == 0) { + ret = au1xxx_dbdma_put_source_flags(psc->tx_chan, + (void *)(unsigned long)runtime->dma_addr + (i * len), + len, + DDMA_FLAGS_IE | DDMA_FLAGS_NOCV); + } else { + ret = au1xxx_dbdma_put_dest_flags(psc->rx_chan, + (void *)(unsigned long)runtime->dma_addr + (i * len), + len, + DDMA_FLAGS_IE | DDMA_FLAGS_NOCV); + } + if (!ret) { + printk(KERN_INFO "au1x-pcm: error adding DMA data\n"); + ret = -EINVAL; + goto out; + } + } + +#ifdef PCM_DEBUG + au1xxx_dbdma_dump(dir ? psc->rx_chan : psc->tx_chan); +#endif + dd->pos = 0; + dd->substream = substream; + dd->period_bytes = len; + dd->periods = segs; + ret = 0; +out: + MSG("pcm_hw_params() leave %d\n", ret); + return ret; +} + +/* + * Free's resources allocated by hw_params, can be called multiple times + */ +static int au1xpsc_pcm_hw_free(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct au1xpsc_pcm *psc = &au1xpsc_pcm_data[rtd->dai->cpu_dai->id]; + struct au1xpsc_pcm_dmadata *dd; + + MSG("pcm_hw_free() enter\n"); + + dd = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? &psc->dma_play + : &psc->dma_rec; + + dd->substream = NULL; + dd->pos = 0; + dd->periods = 0; + dd->period_bytes = 0; + + snd_pcm_lib_free_pages(substream); + + MSG("pcm_hw_free() leave\n"); + return 0; +} + +/* + * Called by ALSA when the PCM substream is prepared, can set format, sample + * rate, etc. This function is non atomic and can be called multiple times, + * it can refer to the runtime info. + */ +static int au1xpsc_pcm_prepare(struct snd_pcm_substream *substream) +{ + MSG("prepare() enter\n"); + MSG("prepare() leave\n"); + return 0; +} + +/* + * Starts (Triggers) audio playback or capture. + * Usually only needed for DMA + */ +static int au1xpsc_pcm_trigger(struct snd_pcm_substream *substream, int cmd) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct au1xpsc_pcm *psc = &au1xpsc_pcm_data[rtd->dai->cpu_dai->id]; + u32 dmachan; + + dmachan = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + ? psc->tx_chan : psc->rx_chan; + + switch (cmd) + { + case SNDRV_PCM_TRIGGER_START: + au1xxx_dbdma_start(dmachan); + break; + case SNDRV_PCM_TRIGGER_STOP: + au1xxx_dbdma_stop(dmachan); + break; + default: + return -EINVAL; + } + return 0; +} + +/* + * Returns the DMA audio frame position + */ +static snd_pcm_uframes_t +au1xpsc_pcm_pointer(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct au1xpsc_pcm *psc = &au1xpsc_pcm_data[rtd->dai->cpu_dai->id]; + int dir; + snd_pcm_uframes_t ret; + unsigned long off; + + dir = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1; + if (dir != 0) { + off = psc->dma_rec.pos; + } else { + off = psc->dma_play.pos; + } + ret = bytes_to_frames(runtime, off); + + return ret; +} + + /* + * Called by ALSA when a PCM substream is opened, private data can be allocated. + */ +static int au1xpsc_pcm_open(struct snd_pcm_substream *substream) +{ + MSG("pcm_open() enter\n"); + + snd_soc_set_runtime_hwparams(substream, &au1xpsc_pcm_hardware); + + MSG("pcm_open() leave\n"); + return 0; +} + +/* + * Called by ALSA when a PCM substream is closed. Private data can be + * freed here. + */ +static int au1xpsc_pcm_close(struct snd_pcm_substream *substream) +{ + MSG("pcm_close() enter\n"); + + MSG("pcm_close() leave\n"); + return 0; +} + +/* ALSA PCM operations */ +struct snd_pcm_ops au1xpsc_pcm_ops = { + .open = au1xpsc_pcm_open, + .close = au1xpsc_pcm_close, + .ioctl = snd_pcm_lib_ioctl, + .hw_params = au1xpsc_pcm_hw_params, + .hw_free = au1xpsc_pcm_hw_free, + .prepare = au1xpsc_pcm_prepare, + .trigger = au1xpsc_pcm_trigger, + .pointer = au1xpsc_pcm_pointer, +}; + +/* + * Called by ASoC core to free platform DMA. + */ +static void au1xpsc_pcm_free_dma_buffers(struct snd_pcm *pcm) +{ + MSG("pcm_free_dma() enter\n"); + snd_pcm_lib_preallocate_free_for_all(pcm); + MSG("pcm_free_dma() leave\n"); +} + +static dbdev_tab_t au1xpsc_mem_dbdev = +{ + DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 16, 0x00000000, 0, 0 +}; + +/* + * Called by the ASoC core to create and initialise the platform DMA. + */ +static int au1xpsc_pcm_new(struct snd_card *card, struct snd_soc_codec_dai *dai, + struct snd_pcm *pcm) +{ + int memid; + struct au1xpsc_pcm *psc = &au1xpsc_pcm_data[1]; /* HACK!!!! */ + + /* + struct platform_device *pdev = to_platform_device(card->dev); + struct au1xpsc_pcm *psc = platform_get_drvdata(pdev); + */ + MSG("pcm_new() enter\n"); + MSG("psc_base 0x%08lx\n", psc->pscbase); + +/* FIXME: THIS STUFF SHOULD BE MOVED TO pcm_open(), and the whole DMA + descriptor ring torn down again in pcm_close(). This is necessary to + support different amounts of periods and/or sampledepths!! +*/ + + snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, NULL, + AU1XPSC_BUFFER_MIN_BYTES, (4096 * 1024) - 1); + + /* allocate DBDMA channels */ + memid = au1xxx_ddma_add_device(&au1xpsc_mem_dbdev); + + psc->tx_chan = au1xxx_dbdma_chan_alloc(memid, psc->dmatx, + au1x_dbdma_tx_callback, (void *)psc); + + psc->rx_chan = au1xxx_dbdma_chan_alloc(psc->dmarx, memid, + au1x_dbdma_rx_callback, (void *)psc); + + /* this needs to be adjusted for the requested bitdepth! */ + au1xxx_dbdma_set_devwidth(psc->tx_chan, 16); + au1xxx_dbdma_set_devwidth(psc->rx_chan, 16); + + au1xxx_dbdma_ring_alloc(psc->tx_chan, AU1XPSC_PERIODS_MIN); + au1xxx_dbdma_ring_alloc(psc->rx_chan, AU1XPSC_PERIODS_MIN); + + MSG("pcm_new() leave\n"); + return 0; +} + +static int au1xpsc_pcm_probe(struct platform_device *pdev) +{ + MSG("probe() enter\n"); + MSG("probe() leave\n"); + return 0; +} + +static int au1xpsc_pcm_remove(struct platform_device *pdev) +{ + MSG("remove() enter\n"); + MSG("remove() leave\n"); + return 0; +} + +/* au1xpsc audio platform */ +struct snd_soc_platform au1xpsc_soc_platform = { + .name = "au1xpsc-pcm-dbdma", + .probe = au1xpsc_pcm_probe, + .remove = au1xpsc_pcm_remove, + .pcm_ops = &au1xpsc_pcm_ops, + .pcm_new = au1xpsc_pcm_new, + .pcm_free = au1xpsc_pcm_free_dma_buffers, +}; +EXPORT_SYMBOL_GPL(au1xpsc_soc_platform); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Au1200/Au1550 Audio DMA driver"); +MODULE_AUTHOR("Manuel Lauss "); diff --git a/sound/soc/au1x/exmmb-ac97.c b/sound/soc/au1x/exmmb-ac97.c new file mode 100644 index 0000000..629e3d2 --- /dev/null +++ b/sound/soc/au1x/exmmb-ac97.c @@ -0,0 +1,200 @@ +/* + * EXM32 Motherboard AC97 sound support; for Au1200 based systems. + * + * Copyright (c) 2007 MSC Vertriebsges.m.b.H, Manuel Lauss + * http://www.exm32.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "../codecs/ac97.h" +#include "psc.h" + +/* #define MACH_DEBUG */ + +#ifdef MACH_DEBUG +#define MSG(x...) printk(KERN_INFO "exmmb-ac97: " x) +#else +#define MSG(x...) do {} while (0) +#endif + +/* + * Alsa operations + * Only implement the required operations for your platform. + * These operations are specific to the machine only. + */ + +/* + * Initialise the machine audio subsystem. + */ +static int exm1200_mobo_ac97_machine_init(struct snd_soc_codec *codec) +{ + snd_soc_dapm_sync(codec); + return 0; +} + +/* template digital audio interface glue - connects codec <--> CPU */ +static struct snd_soc_dai_link exm1200_mobo_ac97_dai = { + .name = "AC97", + .stream_name = "AC97 HiFi", + .cpu_dai = &au1xpsc_ac97_dai[1], /* we use PSC1 for I2S */ + .codec_dai = &ac97_dai, + .init = exm1200_mobo_ac97_machine_init, + .ops = NULL, +}; + +/* template audio machine driver */ +static struct snd_soc_machine snd_soc_machine_exm97 = { + .name = "EXM32 Motherboard AC97", + .dai_link = &exm1200_mobo_ac97_dai, + .num_links = 1, +}; + +/* template audio subsystem */ +static struct snd_soc_device exm1200_mobo_ac97_snd_devdata = { + .machine = &snd_soc_machine_exm97, + .platform = &au1xpsc_soc_platform, + .codec_dev = &soc_codec_dev_ac97, +}; + +static struct resource au1x_psc_res[] = { + [0] = { + .start = PSC1_BASE, + .end = PSC1_BASE + 0xffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 11, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = 16, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = 17, + .flags = IORESOURCE_DMA, + }, +}; + + +static struct platform_device *exm1200_mobo_ac97_snd_device; + +static int psc_to_ac97(void) +{ + unsigned long io; + unsigned int i; + + /* modify sys_pinfunc for AC97 on PSC1 */ + io = au_readl(0xb190002c); + io |= (1<<14); + io &= ~((3<<21)|(1<<20)); + au_writel(io, 0xb190002c); + au_sync(); + + /* AC97 mode */ + io = 0xb1b00000; + (void)au_readl(io + PSC_CTL); + au_writel(0, io + PSC_CTL); + au_writel(0, io + PSC_SEL); + au_sync(); + au_writel(4 | (1<<5), io + PSC_SEL); + + /* cold reset */ + au_writel(2, io + PSC_AC97RST); + au_sync(); + msleep(1200); + au_writel(0, io + PSC_AC97RST); + au_sync(); + + /* enable PSC */ + au_writel(3, io + PSC_CTL); + au_sync(); + + i = 1000; + while (((au_readl(io + PSC_AC97STAT) & 1) == 0) && (--i)) + au_sync(); + + if (i == 0) + printk(KERN_INFO "PSC down!\n"); + + /* en ac97 core */ + au_writel(0x04000000, io + PSC_AC97CFG); + au_sync(); + + i = 1000; + while (((au_readl(io + PSC_AC97STAT) & 2) == 0) && (--i)) + au_sync(); + + if (i == 0) + printk(KERN_INFO "PSC-AC97 not ready\n"); + return (i == 0); +} + +static int exm1200_mobo_ac97_init(void) +{ + int ret = -ENOMEM; + unsigned short brdctl; + + MSG("module_init() enter\n"); + + /* switch FPGA to AC97 mode */ + brdctl = au_readw(EXM1200_FPGA_BRDCTRL); + brdctl &= ~(1 << 13); + au_writew(brdctl, EXM1200_FPGA_BRDCTRL); + au_sync(); + + if (psc_to_ac97()) { + ret = -ENODEV; + goto out; + } + + exm1200_mobo_ac97_snd_device = platform_device_alloc("soc-audio", -1); + if (!exm1200_mobo_ac97_snd_device) + goto out; + + exm1200_mobo_ac97_snd_device->resource = au1x_psc_res; + exm1200_mobo_ac97_snd_device->num_resources = ARRAY_SIZE(au1x_psc_res); + exm1200_mobo_ac97_snd_device->id = 1; + + platform_set_drvdata(exm1200_mobo_ac97_snd_device, &exm1200_mobo_ac97_snd_devdata); + exm1200_mobo_ac97_snd_devdata.dev = &exm1200_mobo_ac97_snd_device->dev; + ret = platform_device_add(exm1200_mobo_ac97_snd_device); + + if (ret) + platform_device_put(exm1200_mobo_ac97_snd_device); + +out: + MSG("module_init() exit (ret %d)\n", ret); + return ret; +} + +static void exm1200_mobo_ac97_exit(void) +{ + platform_device_del(exm1200_mobo_ac97_snd_device); +} + +module_init(exm1200_mobo_ac97_init); +module_exit(exm1200_mobo_ac97_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("MSC EXM32 Development Motherboard AC97 Audio support"); +MODULE_AUTHOR("Manuel Lauss "); diff --git a/sound/soc/au1x/exmmb-i2s.c b/sound/soc/au1x/exmmb-i2s.c new file mode 100644 index 0000000..2e0108d --- /dev/null +++ b/sound/soc/au1x/exmmb-i2s.c @@ -0,0 +1,214 @@ +/* + * EXM32 mobo I2S, for the Crystal CS42518 codec and Au1200 based CPU Modules. + * + * Copyright (c) 2007 MSC Vertriebsges.m.b.H, Manuel Lauss + * see http://www.exm32.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "../codecs/cs4251x.h" +#include "psc.h" + +/* #define MACH_DEBUG */ + +#ifdef MACH_DEBUG +#define MSG(x...) printk(KERN_INFO "exmmb-i2s: " x) +#else +#define MSG(x...) do {} while (0) +#endif + +static int exm1200_mobo_i2s_machine_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_codec_dai *codec_dai = rtd->dai->codec_dai; + struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai; + int ret; + + MSG("machine_hw_params() enter\n"); + + /* set codec and i2s interfaces to slave mode */ + ret = codec_dai->dai_ops.set_fmt(codec_dai, SND_SOC_DAIFMT_LEFT_J | + SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); + if (ret < 0) { + MSG("codec dai setfmt() failed!\n"); + goto out; + } + + ret = codec_dai->dai_ops.set_sysclk(codec_dai, 0, 24576000, 0); + if (ret < 0) { + MSG("codec does not want sysclk\n"); + goto out; + } + + ret = cpu_dai->dai_ops.set_fmt(cpu_dai, SND_SOC_DAIFMT_LEFT_J | + SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); + if (ret < 0) { + MSG("cpu-i2s dai setfmt() failed!\n"); + goto out; + } + + ret = 0; +out: + MSG("machine_hw_params() leave\n"); + return ret; +} + +/* machine Alsa PCM operations */ +static struct snd_soc_ops exm1200_mobo_i2s_ops = { + .hw_params = exm1200_mobo_i2s_machine_hw_params, +}; + +/* + * Initialise the machine audio subsystem. + */ +static int exm1200_mobo_i2s_machine_init(struct snd_soc_codec *codec) +{ + /* EXM32 Motherboard uses the codec in MASTER mode (DSP possible) + * with ADC (recording) data output at the SAI_SDOUT/SAI_SPCLK pins, + * the chip clocked at 24.576 MHz from an external clocksource. + * RXP5/6 determine DAC input source: + * RXP5 ----\ + * RXP6 ---\| + * || + * 00 I2S data from CPU + * 01 DSP + * 10 I2S audio from GSM phone on navi module + * 11 SPDIF input from motherboard/IEEE1394 controller, ... + */ + cs4251x_write(codec, CS4251X_CLKCTL, CS4251X_CLKSRC_AUTO_PLL_OMCK | CS4251X_CLKSRC_OMCK_245760MHZ); + cs4251x_write(codec, CS4251X_FUNCMODE, CS4251X_ADCDAI_SAISDOUT_SAISP_CLK); + cs4251x_write(codec, CS4251X_MUTEC, 0x1f); + cs4251x_write(codec, CS4251X_RCVMODECTL, 0x80); + cs4251x_write(codec, CS4251X_RCVMODECTL2, 0x02); + /* set DAC input to I2S from CPU */ + cs4251x_gpio_mode(codec, CS4251X_RXP_5, CS4251X_GPIO_MODE_GPOLOW, 0, 0); + cs4251x_gpio_mode(codec, CS4251X_RXP_6, CS4251X_GPIO_MODE_GPOLOW, 0, 0); + + /* mark unused codec pins as NC */ + + /* Add template specific controls */ + + /* Add template specific widgets */ + + /* Set up template specific audio path audio_map */ + + /* synchronise subsystem */ + snd_soc_dapm_sync(codec); + + return 0; +} + +static struct snd_soc_dai_link exm1200_mobo_i2s_dai = { + .name = "CS4251X", + .stream_name = "CS4251X", + .cpu_dai = &au1xpsc_i2s_dai[1], /* we use PSC1 for I2S */ + .codec_dai = &cs4251x_dai, + .init = exm1200_mobo_i2s_machine_init, + .ops = &exm1200_mobo_i2s_ops, +}; + +static struct snd_soc_machine snd_soc_machine_template = { + .name = "EXM32 Motherboard I2S", + .dai_link = &exm1200_mobo_i2s_dai, + .num_links = 1, +}; + +/* CS42518 setup data. */ +static struct cs4251x_setup_data exm1200_mobo_i2s_codec_setup = { + .i2c_address = 0x9e >> 1, + .irq = EXMMB_CODEC_IRQ, +}; + +static struct snd_soc_device exm1200_mobo_i2s_snd_devdata = { + .machine = &snd_soc_machine_template, + .platform = &au1xpsc_soc_platform, + .codec_dev = &soc_codec_dev_cs4251x, + .codec_data = &exm1200_mobo_i2s_codec_setup, +}; + +static struct platform_device *exm1200_mobo_i2s_snd_device; + +static struct resource au1x_psc_res[] = { + [0] = { + .start = PSC1_BASE, + .end = PSC1_BASE + 0xffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 11, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = 16, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = 17, + .flags = IORESOURCE_DMA, + }, +}; + +static int exm1200_mobo_i2s_init(void) +{ + int ret = -ENOMEM; + unsigned short brdctl; + + MSG("module_init() enter\n"); + + /* switch FPGA to I2S mode */ + brdctl = au_readw(EXM1200_FPGA_BRDCTRL); + brdctl |= (1 << 13); + au_writew(brdctl, EXM1200_FPGA_BRDCTRL); + au_sync(); + + exm1200_mobo_i2s_snd_device = platform_device_alloc("soc-audio", -1); + if (!exm1200_mobo_i2s_snd_device) + goto out; + + exm1200_mobo_i2s_snd_device->resource = au1x_psc_res; + exm1200_mobo_i2s_snd_device->num_resources = ARRAY_SIZE(au1x_psc_res); + exm1200_mobo_i2s_snd_device->id = 1; + + platform_set_drvdata(exm1200_mobo_i2s_snd_device, &exm1200_mobo_i2s_snd_devdata); + exm1200_mobo_i2s_snd_devdata.dev = &exm1200_mobo_i2s_snd_device->dev; + ret = platform_device_add(exm1200_mobo_i2s_snd_device); + + if (ret) + platform_device_put(exm1200_mobo_i2s_snd_device); + +out: + MSG("module_init() exit (ret %d)\n", ret); + return ret; +} + +static void exm1200_mobo_i2s_exit(void) +{ + platform_device_del(exm1200_mobo_i2s_snd_device); +} + +module_init(exm1200_mobo_i2s_init); +module_exit(exm1200_mobo_i2s_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("MSC EXM32 Development Motherboard I2S Audio support"); +MODULE_AUTHOR("Manuel Lauss "); diff --git a/sound/soc/blackfin/bf548-ezkit.c b/sound/soc/blackfin/bf548-ezkit.c new file mode 100644 index 0000000..17b4cbb --- /dev/null +++ b/sound/soc/blackfin/bf548-ezkit.c @@ -0,0 +1,182 @@ +/* + * bf548_ezkit.c -- SoC audio for bf548 ezkit + * + * Copyright 2007 Analog Device Inc. + * + * Authors: Roy Huang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Revision history + * 8th June 2007 Initial version. + */ + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include "../codecs/ad1980.h" +#include "bf5xx-sport.h" +#include "bf5xx-pcm.h" +#include "bf5xx-ac97.h" + +#define PIN_REQ_SPORT_0 {P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, \ + P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0} + +#define PIN_REQ_SPORT_1 {P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, \ + P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0} + +#define PIN_REQ_SPORT_2 {P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS, \ + P_SPORT2_DRPRI, P_SPORT2_RSCLK, 0} + +#define PIN_REQ_SPORT_3 {P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS, \ + P_SPORT3_DRPRI, P_SPORT3_RSCLK, 0} + + +static int sport_num = CONFIG_SND_BF5XX_SPORT_NUM; + +static struct sport_param sport_params[4] = { + { + .dma_rx_chan = CH_SPORT0_RX, + .dma_tx_chan = CH_SPORT0_TX, + .err_irq = IRQ_SPORT0_ERR, + .regs = (struct sport_register*)SPORT0_TCR1, + }, + { + .dma_rx_chan = CH_SPORT1_RX, + .dma_tx_chan = CH_SPORT1_TX, + .err_irq = IRQ_SPORT1_ERR, + .regs = (struct sport_register*)SPORT1_TCR1, + }, + { + .dma_rx_chan = CH_SPORT2_RX, + .dma_tx_chan = CH_SPORT2_TX, + .err_irq = IRQ_SPORT2_ERR, + .regs = (struct sport_register*)SPORT2_TCR1, + }, + { + .dma_rx_chan = CH_SPORT3_RX, + .dma_tx_chan = CH_SPORT3_TX, + .err_irq = IRQ_SPORT3_ERR, + .regs = (struct sport_register*)SPORT3_TCR1, + } +}; + +struct sport_device *sport_handle; + +static struct snd_soc_machine bf548_ezkit; + +static int bf548_ezkit_startup(struct snd_pcm_substream *substream) +{ + return 0; +} + +static struct snd_soc_ops bf548_ezkit_ops = { + .startup = bf548_ezkit_startup, +}; + +static int bf548_ezkit_ac97_init(struct snd_soc_codec *codec) +{ + return 0; +} + +static struct snd_soc_dai_link bf548_ezkit_dai = { + .name = "AC97", + .stream_name = "AC97 HiFi", + .cpu_dai = &bfin_ac97_dai, + .codec_dai = &ad1980_dai, + .init = bf548_ezkit_ac97_init, + .ops = &bf548_ezkit_ops, +}; + +static int bf548_probe(struct platform_device *pdev) +{ + + u16 sport_req[][7] = {PIN_REQ_SPORT_0, PIN_REQ_SPORT_1, + PIN_REQ_SPORT_2, PIN_REQ_SPORT_3}; + + if (peripheral_request_list(&sport_req[sport_num][0], "soc-audio")) { + printk(KERN_ERR "Requesting Peripherals faild\n"); + return -EFAULT; + } + + /* Request PB3 as reset pin */ + if (gpio_request(GPIO_PB3, NULL)) { + printk(KERN_ERR "Failed to request PB3 for reset\n"); + peripheral_free_list(&sport_req[sport_num][0]); + return -1; + } + gpio_direction_output(GPIO_PB3); + gpio_set_value(GPIO_PB3, 1); + + sport_handle = sport_init(&sport_params[sport_num], 2, \ + 10 * sizeof(struct ac97_frame), NULL); + if (!sport_handle) { + peripheral_free_list(&sport_req[sport_num][0]); + gpio_free(GPIO_PB3); + return -ENODEV; + } + + sport_set_multichannel(sport_handle, 16, 0x1F, 1); + sport_config_rx(sport_handle, IRFS, 0xF, 0, (16*16-1)); + sport_config_tx(sport_handle, ITFS, 0xF, 0, (16*16-1)); + + return 0; +} + +static struct snd_soc_machine bf548_ezkit = { + .name = "bf548-ezkit", + .probe = bf548_probe, + .dai_link = &bf548_ezkit_dai, + .num_links = 1, +}; + +static struct snd_soc_device bf548_ezkit_snd_devdata = { + .machine = &bf548_ezkit, + .platform = &bf5xx_soc_platform, + .codec_dev = &soc_codec_dev_ad1980, +}; + +static struct platform_device *bf548_ezkit_snd_device; + +static int __init bf548_ezkit_init(void) +{ + int ret; + + bf548_ezkit_snd_device = platform_device_alloc("soc-audio", -1); + if (!bf548_ezkit_snd_device) + return -ENOMEM; + + platform_set_drvdata(bf548_ezkit_snd_device, &bf548_ezkit_snd_devdata); + bf548_ezkit_snd_devdata.dev = &bf548_ezkit_snd_device->dev; + ret = platform_device_add(bf548_ezkit_snd_device); + + if (ret) + platform_device_put(bf548_ezkit_snd_device); + + return ret; +} + +static void __exit bf548_ezkit_exit(void) +{ + platform_device_unregister(bf548_ezkit_snd_device); +} + +module_init(bf548_ezkit_init); +module_exit(bf548_ezkit_exit); + +/* Module information */ +MODULE_AUTHOR("Roy Huang"); +MODULE_DESCRIPTION("ALSA SoC BF548-EZKIT"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/blackfin/bf5xx-board.c b/sound/soc/blackfin/bf5xx-board.c new file mode 100644 index 0000000..4acd154 --- /dev/null +++ b/sound/soc/blackfin/bf5xx-board.c @@ -0,0 +1,167 @@ +/* + * bf5xx_board.c -- SoC audio for Blackfin Processors + * + * Copyright 2007 Analog Device Inc. + * + * Authors: Roy Huang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Revision history + * 8th June 2007 Initial version. + */ + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include "../codecs/ad1980.h" +#include "bf5xx-sport.h" +#include "bf5xx-pcm.h" +#include "bf5xx-ac97.h" + +#define PIN_REQ_SPORT_0 {P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, \ + P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0} + +#define PIN_REQ_SPORT_1 {P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, \ + P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0} + + +static int sport_num = CONFIG_SND_BF5XX_SPORT_NUM; + +static struct sport_param sport_params[2] = { + { + .dma_rx_chan = CH_SPORT0_RX, + .dma_tx_chan = CH_SPORT0_TX, + .err_irq = IRQ_SPORT0_ERROR, + .regs = (struct sport_register *)SPORT0_TCR1, + }, + { + .dma_rx_chan = CH_SPORT1_RX, + .dma_tx_chan = CH_SPORT1_TX, + .err_irq = IRQ_SPORT1_ERROR, + .regs = (struct sport_register *)SPORT1_TCR1, + } +}; + +struct sport_device *sport_handle; + +static struct snd_soc_machine bf5xx_board; + +static int bf5xx_board_startup(struct snd_pcm_substream *substream) +{ + return 0; +} + +static struct snd_soc_ops bf5xx_board_ops = { + .startup = bf5xx_board_startup, +}; + +static int bf5xx_board_ac97_init(struct snd_soc_codec *codec) +{ + return 0; +} + +static struct snd_soc_dai_link bf5xx_board_dai = { + .name = "AC97", + .stream_name = "AC97 HiFi", + .cpu_dai = &bfin_ac97_dai, + .codec_dai = &ad1980_dai, + .init = bf5xx_board_ac97_init, + .ops = &bf5xx_board_ops, +}; + +static int bf5xx_probe(struct platform_device *pdev) +{ + + u16 sport_req[][7] = {PIN_REQ_SPORT_0, PIN_REQ_SPORT_1}; + + if (peripheral_request_list(&sport_req[sport_num][0], "soc-audio")) { + printk(KERN_ERR "Requesting Peripherals faild\n"); + return -EFAULT; + } + +#ifdef CONFIG_SND_BF5XX_HAVE_COLD_RESET + /* Request PB3 as reset pin */ + if (gpio_request(CONFIG_SND_BF5XX_RESET_GPIO_NUM, "SND_AD198x RESET")) { + printk(KERN_ERR "Failed to request GPIO_%d for reset\n", + CONFIG_SND_BF5XX_RESET_GPIO_NUM); + peripheral_free_list(&sport_req[sport_num][0]); + return -1; + } + gpio_direction_output(CONFIG_SND_BF5XX_RESET_GPIO_NUM); + gpio_set_value(CONFIG_SND_BF5XX_RESET_GPIO_NUM, 1); +#endif + sport_handle = sport_init(&sport_params[sport_num], 2, \ + 10 * sizeof(struct ac97_frame), NULL); + if (!sport_handle) { + peripheral_free_list(&sport_req[sport_num][0]); +#ifdef CONFIG_SND_BF5XX_HAVE_COLD_RESET + gpio_free(CONFIG_SND_BF5XX_RESET_GPIO_NUM); +#endif + return -ENODEV; + } + + sport_set_multichannel(sport_handle, 16, 0x1F, 1); + sport_config_rx(sport_handle, IRFS, 0xF, 0, (16*16-1)); + sport_config_tx(sport_handle, ITFS, 0xF, 0, (16*16-1)); + + return 0; +} + +static struct snd_soc_machine bf5xx_board = { + .name = "bf5xx-board", + .probe = bf5xx_probe, + .dai_link = &bf5xx_board_dai, + .num_links = 1, +}; + +static struct snd_soc_device bf5xx_board_snd_devdata = { + .machine = &bf5xx_board, + .platform = &bf5xx_soc_platform, + .codec_dev = &soc_codec_dev_ad1980, +}; + +static struct platform_device *bf5xx_board_snd_device; + +static int __init bf5xx_board_init(void) +{ + int ret; + + bf5xx_board_snd_device = platform_device_alloc("soc-audio", -1); + if (!bf5xx_board_snd_device) + return -ENOMEM; + + platform_set_drvdata(bf5xx_board_snd_device, &bf5xx_board_snd_devdata); + bf5xx_board_snd_devdata.dev = &bf5xx_board_snd_device->dev; + ret = platform_device_add(bf5xx_board_snd_device); + + if (ret) + platform_device_put(bf5xx_board_snd_device); + + return ret; +} + +static void __exit bf5xx_board_exit(void) +{ + platform_device_unregister(bf5xx_board_snd_device); +} + +module_init(bf5xx_board_init); +module_exit(bf5xx_board_exit); + +/* Module information */ +MODULE_AUTHOR("Roy Huang"); +MODULE_DESCRIPTION("ALSA SoC BF5xx Board"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/blackfin/bf5xx-pcm.c b/sound/soc/blackfin/bf5xx-pcm.c new file mode 100644 index 0000000..a87e807 --- /dev/null +++ b/sound/soc/blackfin/bf5xx-pcm.c @@ -0,0 +1,285 @@ +/* + * linux/sound/arm/bf5xx-pcm.c -- ALSA PCM interface for the Blackfin + * + * Author: Roy Huang + * Copyright: (C) 2007 Analog Device Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include "bf5xx-pcm.h" +#include "bf5xx-ac97.h" +#include "bf5xx-sport.h" + + +static void bf5xx_dma_irq(void *data) +{ + struct snd_pcm_substream *pcm = data; + + pr_debug("%s enter \n", __FUNCTION__); + snd_pcm_period_elapsed(pcm); +} + +/* The memory size for pure pcm data is 128*1024 = 0x20000 bytes. + * The total rx/tx buffer is for ac97 frame to hold all pcm data + * is 0x20000 * sizeof(struct ac97_frame) / 4. + */ +static const struct snd_pcm_hardware bf5xx_pcm_hardware = { + .info = SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_BLOCK_TRANSFER, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + .period_bytes_min = 32, + .period_bytes_max = 0x10000, + .periods_min = 1, + .periods_max = PAGE_SIZE/32, + .buffer_bytes_max = 0x20000, /* 128 kbytes */ + .fifo_size = 16, +}; + +static int bf5xx_pcm_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + size_t size = bf5xx_pcm_hardware.buffer_bytes_max * \ + sizeof(struct ac97_frame) / 4; + + snd_pcm_lib_malloc_pages(substream, size); + + return 0; +} + +static int bf5xx_pcm_hw_free(struct snd_pcm_substream *substream) +{ + snd_pcm_lib_free_pages(substream); + return 0; +} + +static int bf5xx_pcm_prepare(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct sport_device *sport = runtime->private_data; + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + sport_set_tx_callback(sport, bf5xx_dma_irq, substream); + sport_config_tx_dma(sport, runtime->dma_area, runtime->periods, + runtime->period_size * sizeof(struct ac97_frame)); + } else { + sport_set_rx_callback(sport, bf5xx_dma_irq, substream); + sport_config_rx_dma(sport, runtime->dma_area, runtime->periods, + runtime->period_size * sizeof(struct ac97_frame)); + } + return 0; +} + +static int bf5xx_pcm_trigger(struct snd_pcm_substream *substream, int cmd) +{ + struct sport_device *sport = substream->runtime->private_data; + int ret = 0; + + pr_debug("%s %s\n", substream->stream?"Capture":"Playback", \ + cmd?" start":" stop"); + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + sport_tx_start(sport); + else + sport_rx_start(sport); + break; + + case SNDRV_PCM_TRIGGER_STOP: + case SNDRV_PCM_TRIGGER_SUSPEND: + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + pr_debug("stop dma\n"); + sport_tx_stop(sport); + } else + sport_rx_stop(sport); + break; + + default: + ret = -EINVAL; + } + + return ret; +} + +static snd_pcm_uframes_t bf5xx_pcm_pointer(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct sport_device *sport = runtime->private_data; + unsigned int curr; + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + curr = sport_curr_offset_tx(sport) / sizeof(struct ac97_frame); + else + curr = sport_curr_offset_rx(sport) / sizeof(struct ac97_frame); + pr_debug("%s pointer curr:0x%0x\n", substream->stream ? \ + "Capture":"Playback", curr); + + return curr; +} + +static int bf5xx_pcm_copy(struct snd_pcm_substream *substream, int channel, + snd_pcm_uframes_t pos, + void __user *buf, snd_pcm_uframes_t count) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + + pr_debug("%s copy pos:0x%lx count:0x%lx\n", + substream->stream?"Capture":"Playback", pos, count); + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + bf5xx_ac97_pcm32_to_frame( + (struct ac97_frame *)runtime->dma_area + pos, + buf, count); + } else + bf5xx_ac97_frame_to_pcm32( + (struct ac97_frame *)runtime->dma_area + pos, + buf, count); + + return 0; +} + +static int bf5xx_pcm_open(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + int ret; + + pr_debug("%s enter\n", __FUNCTION__); + snd_soc_set_runtime_hwparams(substream, &bf5xx_pcm_hardware); + + ret = snd_pcm_hw_constraint_integer(runtime, \ + SNDRV_PCM_HW_PARAM_PERIODS); + if (ret < 0) + goto out; + + if (sport_handle != NULL) + runtime->private_data = sport_handle; + else { + printk(KERN_ERR "sport_handle is NULL\n"); + return -1; + } + return 0; + + out: + return ret; +} + +static int bf5xx_pcm_close(struct snd_pcm_substream *substream) +{ + return 0; +} + +struct snd_pcm_ops bf5xx_pcm_ops = { + .open = bf5xx_pcm_open, + .close = bf5xx_pcm_close, + .ioctl = snd_pcm_lib_ioctl, + .hw_params = bf5xx_pcm_hw_params, + .hw_free = bf5xx_pcm_hw_free, + .prepare = bf5xx_pcm_prepare, + .trigger = bf5xx_pcm_trigger, + .pointer = bf5xx_pcm_pointer, + .copy = bf5xx_pcm_copy, +}; + +static int bf5xx_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream) +{ + struct snd_pcm_substream *substream = pcm->streams[stream].substream; + struct snd_dma_buffer *buf = &substream->dma_buffer; + size_t size = bf5xx_pcm_hardware.buffer_bytes_max * \ + sizeof(struct ac97_frame) / 4; + + buf->dev.type = SNDRV_DMA_TYPE_DEV; + buf->dev.dev = pcm->card->dev; + buf->private_data = NULL; + buf->area = dma_alloc_coherent(pcm->card->dev, size, &buf->addr, GFP_KERNEL); + if (!buf->area) { + printk(KERN_ERR "Failed to allocate dma memory\n"); + return -ENOMEM; + } + buf->bytes = size; + + pr_debug("%s, area:%p, size:0x%08lx\n", __FUNCTION__, buf->area, buf->bytes); + if (stream == SNDRV_PCM_STREAM_PLAYBACK) + sport_handle->tx_buf = buf->area; + else + sport_handle->rx_buf = buf->area; + + return 0; +} + +static void bf5xx_pcm_free_dma_buffers(struct snd_pcm *pcm) +{ + struct snd_pcm_substream *substream; + struct snd_dma_buffer *buf; + int stream; + + for (stream = 0; stream < 2; stream++) { + substream = pcm->streams[stream].substream; + if (!substream) + continue; + + buf = &substream->dma_buffer; + if (!buf->area) + continue; + + dma_free_coherent(NULL, buf->bytes, buf->area, 0); + buf->area = NULL; + } +} + +static u64 bf5xx_pcm_dmamask = DMA_32BIT_MASK; + +int bf5xx_pcm_new(struct snd_card *card, struct snd_soc_codec_dai *dai, + struct snd_pcm *pcm) +{ + int ret = 0; + + pr_debug("%s enter\n", __FUNCTION__); + if (!card->dev->dma_mask) + card->dev->dma_mask = &bf5xx_pcm_dmamask; + if (!card->dev->coherent_dma_mask) + card->dev->coherent_dma_mask = DMA_32BIT_MASK; + + if (dai->playback.channels_min) { + ret = bf5xx_pcm_preallocate_dma_buffer(pcm, + SNDRV_PCM_STREAM_PLAYBACK); + if (ret) + goto out; + } + + if (dai->capture.channels_min) { + ret = bf5xx_pcm_preallocate_dma_buffer(pcm, + SNDRV_PCM_STREAM_CAPTURE); + if (ret) + goto out; + } + out: + return ret; +} + +struct snd_soc_platform bf5xx_soc_platform = { + .name = "bf5xx-audio", + .pcm_ops = &bf5xx_pcm_ops, + .pcm_new = bf5xx_pcm_new, + .pcm_free = bf5xx_pcm_free_dma_buffers, +}; +EXPORT_SYMBOL_GPL(bf5xx_soc_platform); + +MODULE_AUTHOR("Roy Huang"); +MODULE_DESCRIPTION("ADI Blackfin PCM DMA module"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/blackfin/bf5xx-pcm.h b/sound/soc/blackfin/bf5xx-pcm.h new file mode 100644 index 0000000..75e6829 --- /dev/null +++ b/sound/soc/blackfin/bf5xx-pcm.h @@ -0,0 +1,29 @@ +/* + * linux/sound/arm/bf5xx-pcm.h -- ALSA PCM interface for the Blackfin + * + * Copyright 2007 Analog Device Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _BF5XX_PCM_H +#define _BF5XX_PCM_H + +struct bf5xx_pcm_dma_params { + char *name; /* stream identifier */ +}; + +struct bf5xx_gpio { + u32 sys; + u32 rx; + u32 tx; + u32 clk; + u32 frm; +}; + +/* platform data */ +extern struct snd_soc_platform bf5xx_soc_platform; + +#endif diff --git a/sound/soc/blackfin/bf5xx-wm8750.c b/sound/soc/blackfin/bf5xx-wm8750.c new file mode 100644 index 0000000..4e0d2ab --- /dev/null +++ b/sound/soc/blackfin/bf5xx-wm8750.c @@ -0,0 +1,260 @@ +/* + * bf5xx_wm8750.c -- SoC audio for bf5xx WM8750 + * + * Copyright 2007 Analog Device Inc. + * Copyright 2007 Wolfson Microelectronics PLC + * + * Based on bf548_ezkit.c by Roy Huang + * + * Authors: Liam Girdwood + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Revision history + * 29th Aug 2007 Initial version. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include "../codecs/wm8750.h" +#include "bf5xx-sport.h" +#include "bf5xx-pcm.h" +#include "bf5xx-i2s.h" + +#define BF53X_WM8750_DEBUG + +#ifdef BF53X_WM8750_DEBUG +#define printd(format, arg...) printk("bfin-wm8750: " format, ## arg) +#endif + + +#define PIN_REQ_SPORT_0 {P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, \ + P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0} + +#define PIN_REQ_SPORT_1 {P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, \ + P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0} + +#define PIN_REQ_SPORT_2 {P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS, \ + P_SPORT2_DRPRI, P_SPORT2_RSCLK, 0} + +#define PIN_REQ_SPORT_3 {P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS, \ + P_SPORT3_DRPRI, P_SPORT3_RSCLK, 0} + + +static int sport_num = CONFIG_SND_BF5XX_SPORT_NUM; + +static struct sport_param sport_params[4] = { + { + .dma_rx_chan = CH_SPORT0_RX, + .dma_tx_chan = CH_SPORT0_TX, + .err_irq = IRQ_SPORT0_ERR, + .regs = (struct sport_register*)SPORT0_TCR1, + }, + { + .dma_rx_chan = CH_SPORT1_RX, + .dma_tx_chan = CH_SPORT1_TX, + .err_irq = IRQ_SPORT1_ERR, + .regs = (struct sport_register*)SPORT1_TCR1, + }, + { + .dma_rx_chan = CH_SPORT2_RX, + .dma_tx_chan = CH_SPORT2_TX, + .err_irq = IRQ_SPORT2_ERR, + .regs = (struct sport_register*)SPORT2_TCR1, + }, + { + .dma_rx_chan = CH_SPORT3_RX, + .dma_tx_chan = CH_SPORT3_TX, + .err_irq = IRQ_SPORT3_ERR, + .regs = (struct sport_register*)SPORT3_TCR1, + } +}; + +struct sport_device *sport_handle; + +static struct snd_soc_machine bf5xx_wm8750; + +static int bf5xx_wm8750_startup(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai; + + cpu_dai->private_data = sport_handle; + return 0; +} + +static int bf5xx_wm8750_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_codec_dai *codec_dai = rtd->dai->codec_dai; + struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai; + unsigned int clk = 0; + int ret = 0; + + printd("%s rate %d format %x\n", __func__, params_rate(params), + params_format(params)); + /* + * WARNING - TODO + * + * This code assumes there is a variable clocksource for the WM8750. + * i.e. it supplies MCLK depending on rate. + * + * If you are using a crystal source then modify the below case + * statement with a static frequency. + * + * If you are using the SPORT to generate clocking then this is + * where to do it. + */ + + switch (params_rate(params)) { + case 8000: + case 16000: + case 48000: + case 96000: + clk = 12288000; + break; + case 11025: + case 22050: + case 44100: + clk = 11289600; + break; + } + + /* + * CODEC is master for BCLK and LRC in this configuration. + */ + + /* set codec DAI configuration */ + ret = codec_dai->dai_ops.set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | + SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); + if (ret < 0) + return ret; + + /* set cpu DAI configuration */ + ret = cpu_dai->dai_ops.set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | + SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); + if (ret < 0) + return ret; + + /* set the codec system clock for DAC and ADC */ + ret = codec_dai->dai_ops.set_sysclk(codec_dai, WM8750_SYSCLK, clk, + SND_SOC_CLOCK_IN); + if (ret < 0) + return ret; + + return 0; +} + +static struct snd_soc_ops bf5xx_wm8750_ops = { + .startup = bf5xx_wm8750_startup, + .hw_params = bf5xx_wm8750_hw_params, +}; + +static int bf5xx_wm8750_init_dev(struct snd_soc_codec *codec) +{ + /* + * NC codec pins - + * Add any NC codec pins as follows :- + * + * snd_soc_dapm_disable_pin(codec, "RINPUT1"); + */ + printd("%s\n", __func__); + snd_soc_dapm_sync(codec); + return 0; +} + +static struct snd_soc_dai_link bf5xx_wm8750_dai = { + .name = "wm8750", + .stream_name = "WM8750", + .cpu_dai = &bf5xx_i2s_dai[CONFIG_SND_BF5XX_SPORT_NUM], + .codec_dai = &wm8750_dai, + .init = bf5xx_wm8750_init_dev, + .ops = &bf5xx_wm8750_ops, +}; + +static int bf5xx_probe(struct platform_device *pdev) +{ + + u16 sport_req[][7] = {PIN_REQ_SPORT_0, PIN_REQ_SPORT_1, + PIN_REQ_SPORT_2, PIN_REQ_SPORT_3}; + + printd("%s\n", __func__); + if (peripheral_request_list(&sport_req[sport_num][0], "soc-audio")) { + printk(KERN_ERR "Requesting Peripherals faild\n"); + return -EFAULT; + } + + /* TODO: not sure of correct dummy size */ + sport_handle = sport_init(&sport_params[sport_num], 2, \ + 10 * sizeof(u16), NULL); + if (!sport_handle) { + peripheral_free_list(&sport_req[sport_num][0]); + return -ENODEV; + } + + return 0; +} + +static struct snd_soc_machine bf5xx_wm8750 = { + .name = "bf5xx-wm8750", + .probe = bf5xx_probe, + .dai_link = &bf5xx_wm8750_dai, + .num_links = 1, +}; + +static struct snd_soc_device bf5xx_wm8750_snd_devdata = { + .machine = &bf5xx_wm8750, + .platform = &bf5xx_soc_platform, + .codec_dev = &soc_codec_dev_wm8750, +}; + +static struct platform_device *bf54xx_wm8750_snd_device; + +static int __init bf5xx_wm8750_init(void) +{ + int ret; + + printd("%s\n", __func__); + bf54xx_wm8750_snd_device = platform_device_alloc("soc-audio", -1); + if (!bf54xx_wm8750_snd_device) + return -ENOMEM; + + platform_set_drvdata(bf54xx_wm8750_snd_device, &bf5xx_wm8750_snd_devdata); + bf5xx_wm8750_snd_devdata.dev = &bf54xx_wm8750_snd_device->dev; + ret = platform_device_add(bf54xx_wm8750_snd_device); + + if (ret) + platform_device_put(bf54xx_wm8750_snd_device); + + return ret; +} + +static void __exit bf5xx_wm8750_exit(void) +{ + printd("%s\n", __func__); + platform_device_unregister(bf54xx_wm8750_snd_device); +} + +module_init(bf5xx_wm8750_init); +module_exit(bf5xx_wm8750_exit); + +/* Module information */ +MODULE_AUTHOR("Roy Huang"); +MODULE_DESCRIPTION("ALSA SoC BF548-EZKIT"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index d0e0d69..9f33c07 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -11,9 +11,11 @@ config SND_SOC_I2C_AND_SPI config SND_SOC_ALL_CODECS tristate "Build all ASoC CODEC drivers" select SND_SOC_AC97_CODEC if SND_SOC_AC97_BUS + select SND_SOC_AD1939 if I2C select SND_SOC_AD1980 if SND_SOC_AC97_BUS select SND_SOC_AD73311 if I2C select SND_SOC_AK4535 if I2C + select SND_SOC_CS4251X if I2C select SND_SOC_CS4270 if I2C select SND_SOC_PCM3008 select SND_SOC_SSM2602 if I2C @@ -26,14 +28,25 @@ config SND_SOC_ALL_CODECS select SND_SOC_WM8350 if MFD_WM8350 select SND_SOC_WM8510 if SND_SOC_I2C_AND_SPI select SND_SOC_WM8580 if I2C + select SND_SOC_WM8711 if I2C select SND_SOC_WM8728 if SND_SOC_I2C_AND_SPI select SND_SOC_WM8731 if SND_SOC_I2C_AND_SPI select SND_SOC_WM8750 if SND_SOC_I2C_AND_SPI select SND_SOC_WM8753 if SND_SOC_I2C_AND_SPI + select SND_SOC_WM8772 if SPI_MASTER select SND_SOC_WM8900 if I2C select SND_SOC_WM8903 if I2C + select SND_SOC_WM8950 if I2C + select SND_SOC_WM8956 if I2C + select SND_SOC_WM8960 if I2C select SND_SOC_WM8971 if I2C + select SND_SOC_WM8974 if I2C + select SND_SOC_WM8976 if I2C + select SND_SOC_WM8978 if I2C + select SND_SOC_WM8980 if I2C select SND_SOC_WM8990 if I2C + select SND_SOC_WM8991 if I2C + select SND_SOC_WM9705 if SND_SOC_AC97_BUS select SND_SOC_WM9712 if SND_SOC_AC97_BUS select SND_SOC_WM9713 if SND_SOC_AC97_BUS help @@ -47,10 +60,11 @@ config SND_SOC_ALL_CODECS If unsure select "N". - config SND_SOC_AC97_CODEC tristate - select SND_AC97_CODEC + +config SND_SOC_AD1939 + tristate config SND_SOC_AD1980 tristate @@ -61,6 +75,9 @@ config SND_SOC_AD73311 config SND_SOC_AK4535 tristate +config SND_SOC_CS4251X + tristate + # Cirrus Logic CS4270 Codec config SND_SOC_CS4270 tristate @@ -109,7 +126,7 @@ config SND_SOC_UDA134X select SND_SOC_L3 config SND_SOC_UDA1380 - tristate + tristate config SND_SOC_WM8350 tristate @@ -120,6 +137,9 @@ config SND_SOC_WM8510 config SND_SOC_WM8580 tristate +config SND_SOC_WM8711 + tristate + config SND_SOC_WM8728 tristate @@ -132,18 +152,48 @@ config SND_SOC_WM8750 config SND_SOC_WM8753 tristate +config SND_SOC_WM8772 + tristate + config SND_SOC_WM8900 tristate config SND_SOC_WM8903 tristate +config SND_SOC_WM8950 + tristate + +config SND_SOC_WM8956 + tristate + +config SND_SOC_WM8960 + tristate + config SND_SOC_WM8971 tristate +config SND_SOC_WM8974 + tristate + +config SND_SOC_WM8976 + tristate + +config SND_SOC_WM8978 + tristate + +config SND_SOC_WM8980 + tristate + config SND_SOC_WM8990 tristate +config SND_SOC_WM8991 + tristate + +config SND_SOC_WM9705 + tristate + config SND_SOC_WM9712 tristate diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index c4ddc9a..9c61037 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -1,7 +1,10 @@ snd-soc-ac97-objs := ac97.o +snd-soc-ad1939-objs := ad1939.o snd-soc-ad1980-objs := ad1980.o +snd-soc-ak4535-objs := ak4535.o snd-soc-ad73311-objs := ad73311.o snd-soc-ak4535-objs := ak4535.o +snd-soc-cs4251x-objs := cs4251x.o snd-soc-cs4270-objs := cs4270.o snd-soc-l3-objs := l3.o snd-soc-pcm3008-objs := pcm3008.o @@ -15,21 +18,35 @@ snd-soc-uda1380-objs := uda1380.o snd-soc-wm8350-objs := wm8350.o snd-soc-wm8510-objs := wm8510.o snd-soc-wm8580-objs := wm8580.o +snd-soc-wm8711-objs := wm8711.o snd-soc-wm8728-objs := wm8728.o snd-soc-wm8731-objs := wm8731.o snd-soc-wm8750-objs := wm8750.o snd-soc-wm8753-objs := wm8753.o +snd-soc-wm8772-objs := wm8772.o snd-soc-wm8900-objs := wm8900.o snd-soc-wm8903-objs := wm8903.o +snd-soc-wm8950-objs := wm8950.o +snd-soc-wm8951-objs := wm8951.o +snd-soc-wm8956-objs := wm8956.o +snd-soc-wm8960-objs := wm8960.o snd-soc-wm8971-objs := wm8971.o +snd-soc-wm8974-objs := wm8974.o +snd-soc-wm8976-objs := wm8976.o +snd-soc-wm8978-objs := wm8978.o +snd-soc-wm8980-objs := wm8980.o snd-soc-wm8990-objs := wm8990.o +snd-soc-wm8991-objs := wm8991.o +snd-soc-wm9705-objs := wm9705.o snd-soc-wm9712-objs := wm9712.o snd-soc-wm9713-objs := wm9713.o obj-$(CONFIG_SND_SOC_AC97_CODEC) += snd-soc-ac97.o +obj-$(CONFIG_SND_SOC_AD1939) += snd-soc-ad1939.o obj-$(CONFIG_SND_SOC_AD1980) += snd-soc-ad1980.o obj-$(CONFIG_SND_SOC_AD73311) += snd-soc-ad73311.o obj-$(CONFIG_SND_SOC_AK4535) += snd-soc-ak4535.o +obj-$(CONFIG_SND_SOC_CS4251X) += snd-soc-cs4251x.o obj-$(CONFIG_SND_SOC_CS4270) += snd-soc-cs4270.o obj-$(CONFIG_SND_SOC_L3) += snd-soc-l3.o obj-$(CONFIG_SND_SOC_PCM3008) += snd-soc-pcm3008.o @@ -43,13 +60,25 @@ obj-$(CONFIG_SND_SOC_UDA1380) += snd-soc-uda1380.o obj-$(CONFIG_SND_SOC_WM8350) += snd-soc-wm8350.o obj-$(CONFIG_SND_SOC_WM8510) += snd-soc-wm8510.o obj-$(CONFIG_SND_SOC_WM8580) += snd-soc-wm8580.o +obj-$(CONFIG_SND_SOC_WM8711) += snd-soc-wm8711.o obj-$(CONFIG_SND_SOC_WM8728) += snd-soc-wm8728.o obj-$(CONFIG_SND_SOC_WM8731) += snd-soc-wm8731.o obj-$(CONFIG_SND_SOC_WM8750) += snd-soc-wm8750.o obj-$(CONFIG_SND_SOC_WM8753) += snd-soc-wm8753.o +obj-$(CONFIG_SND_SOC_WM8772) += snd-soc-wm8772.o obj-$(CONFIG_SND_SOC_WM8900) += snd-soc-wm8900.o obj-$(CONFIG_SND_SOC_WM8903) += snd-soc-wm8903.o +obj-$(CONFIG_SND_SOC_WM8950) += snd-soc-wm8950.o +obj-$(CONFIG_SND_SOC_WM8951) += snd-soc-wm8951.o +obj-$(CONFIG_SND_SOC_WM8956) += snd-soc-wm8956.o +obj-$(CONFIG_SND_SOC_WM8960) += snd-soc-wm8960.o obj-$(CONFIG_SND_SOC_WM8971) += snd-soc-wm8971.o +obj-$(CONFIG_SND_SOC_WM8974) += snd-soc-wm8974.o +obj-$(CONFIG_SND_SOC_WM8976) += snd-soc-wm8976.o +obj-$(CONFIG_SND_SOC_WM8978) += snd-soc-wm8978.o +obj-$(CONFIG_SND_SOC_WM8980) += snd-soc-wm8980.o obj-$(CONFIG_SND_SOC_WM8990) += snd-soc-wm8990.o +obj-$(CONFIG_SND_SOC_WM8991) += snd-soc-wm8991.o +obj-$(CONFIG_SND_SOC_WM9705) += snd-soc-wm9705.o obj-$(CONFIG_SND_SOC_WM9712) += snd-soc-wm9712.o obj-$(CONFIG_SND_SOC_WM9713) += snd-soc-wm9713.o diff --git a/sound/soc/codecs/ad1939.c b/sound/soc/codecs/ad1939.c new file mode 100644 index 0000000..caa371b --- /dev/null +++ b/sound/soc/codecs/ad1939.c @@ -0,0 +1,679 @@ +/* + * AD1939 I2S Codec driver + * + * (c) 2007 MSC Vertriebsges.m.b.H, + * + * licensed under the GPLv2 + */ + +/* + * Analog Devices AD1939 I2S codec; with I2C or SPI interface. + * supports 2 channels in plain I2S mode, + * and up to 16 channels in TDM modes. + * As Master, the codec always assumes a frame is a multiple of 32bits! + * TDM Modes: + * - multiple channels over I2S + * - 32 fixed slot width, TDM stereo is I2S with 32bits/sample. + * + * TODO: driver switches between stereo and TDM mode based on the number + * of channels for record / playback (ad1939_hw_params()). This + * should be overhauled if someone wants to daisy-chain a few of + * these together (to get 8 DAC channels total). Maybe use TDM + * mode exclusively when codec is LRCK/BCK master, and let the + * user set WHICH TDM mode to use through setup_data. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ad1939.h" + +#define AUDIO_NAME "AD1939" + +struct ad1939_private { + struct snd_soc_codec *codec; + unsigned long sysclk; + unsigned char tdm_mode; +}; + +/* default register contents after reset */ +static const u16 ad1939_regcache[AD1939_REGCOUNT] __devinitdata = { + 0, 0, 0, 0, 0, 0, 255, 255, 255, 255, 255, 255, 255, 255, 0, 0, 0 +}; + +#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) +static int ad1939_i2c_write(struct snd_soc_codec *codec, unsigned int r, + unsigned int v) +{ + struct i2c_msg msg; + struct i2c_client *c; + u8 data[2]; + u16 *cache = codec->reg_cache; + int ret; + + if (cache[r] == v) + return 0; + + /* oh noes, now we have to talk to the codec */ + c = (struct i2c_client *)codec->control_data; + data[0] = r & 0xff; + data[1] = v & 0xff; + msg.addr = c->addr; + msg.flags = 0; /* write */ + msg.buf = &data[0]; + msg.len = 2; + + ret = i2c_transfer(c->adapter, &msg, 1); + if (ret == 1) + cache[r] = v; + return (ret == 1) ? 0 : -EIO; +} + +static unsigned int ad1939_i2c_read(struct snd_soc_codec *codec, + unsigned int r) +{ + struct i2c_msg msg[2]; + struct i2c_client *c; + u16 *cache = codec->reg_cache; + u8 data[2]; + int ret; + + /* the PLLCTL1 has one read-only bit: PLL lock indicator. + * all other regs keep what was set + */ + if (likely(r != AD1939_PLLCTL1)) + return cache[r]; + + c = (struct i2c_client *)codec->control_data; + data[0] = r & 0xff; + msg[0].addr = c->addr; + msg[0].flags = 0; + msg[0].buf = &data[0]; + msg[0].len = 1; + + msg[1].addr = c->addr; + msg[1].flags = I2C_M_RD; + msg[1].buf = &data[1]; + msg[1].len = 1; + + ret = i2c_transfer(c->adapter, &msg[0], 2); + return (ret == 2) ? data[1] : -EIO; +} +#endif + +static inline unsigned int ad1939_read(struct snd_soc_codec *codec, + unsigned int r) +{ + return codec->read(codec, r); +} + +static inline int ad1939_write(struct snd_soc_codec *codec, + unsigned int r, unsigned int v) +{ + return codec->write(codec, r, v); +} + +/***** controls ******/ + +static const char *dac_deemph[] = {"Flat", "48kHz", "44.1kHz", "32kHz"}; +static const char *dac_outpol[] = {"Normal", "Inverted"}; + +static const struct soc_enum ad1939_enum[] = { + /*SOC_ENUM_SINGLE(register, startbit, choices, choices-texts) */ + SOC_ENUM_SINGLE(AD1939_DACCTL2, 1, 4, dac_deemph), + SOC_ENUM_SINGLE(AD1939_DACCTL2, 5, 1, dac_outpol), +}; + +static const struct snd_kcontrol_new ad1939_snd_ctls[] = { +SOC_DOUBLE_R("Master Playback", AD1939_VOL1L, AD1939_VOL1R, 0, 255, 1), +SOC_DOUBLE_R("Channel 2 Playback", AD1939_VOL2L, AD1939_VOL2R, 0, 255, 1), +SOC_DOUBLE_R("Channel 3 Playback", AD1939_VOL3L, AD1939_VOL3R, 0, 255, 1), +SOC_DOUBLE_R("Channel 4 Playback", AD1939_VOL4L, AD1939_VOL4R, 0, 255, 1), +SOC_ENUM("DAC Deemphasis", ad1939_enum[0]), +SOC_ENUM("DAC output polarity", ad1939_enum[1]), +}; + +/* add non dapm controls */ +static int ad1939_add_controls(struct snd_soc_codec *codec) +{ + int err, i; + + for (i = 0; i < ARRAY_SIZE(ad1939_snd_ctls); i++) { + err = snd_ctl_add(codec->card, + snd_soc_cnew(&ad1939_snd_ctls[i], codec, NULL)); + if (err < 0) + return err; + } + return 0; +} + + +/***** chip interface config ******/ + + +static int ad1939_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->codec; + struct ad1939_private *ad = codec->private_data; + unsigned char dac0, dac1, dac2, adc0, adc1, adc2; + unsigned long rate; + unsigned int bits; + + pr_debug("ad1939_hw_params"); + + dac0 = ad1939_read(codec, AD1939_DACCTL0); + dac1 = ad1939_read(codec, AD1939_DACCTL1); + dac2 = ad1939_read(codec, AD1939_DACCTL2); + adc0 = ad1939_read(codec, AD1939_ADCCTL0); + adc1 = ad1939_read(codec, AD1939_ADCCTL1); + adc2 = ad1939_read(codec, AD1939_ADCCTL2); + + rate = params_rate(params); + bits = params->msbits; + + pr_debug("bits %d srate %lu/%d chans %d\n", bits, rate, + params->rate_den, params_channels(params)); + + /* + * sample rate + */ + dac0 &= ~(3<<1); /* 48kHz */ + adc0 &= ~(3<<6); /* 48kHz */ + switch (rate) { + case 32000 ... 48000: + break; + case 64000 ... 96000: + dac0 |= (1<<1); + adc0 |= (1<<6); + break; + case 128000 ... 192000: + dac0 |= (2<<1); + adc0 |= (2<<6); + break; + default: + pr_debug("rejecting srate %lu\n", rate); + return -EINVAL; + } + + /* + * sample width (bits) + */ + dac2 &= ~(3<<3); /* 24 bits */ + adc1 &= ~(3<<0); /* 24 bits */ + switch (bits) { + case 16: dac2 |= (3<<3); adc1 |= (3<<0); break; + case 20: dac2 |= (1<<3); adc1 |= (1<<0); break; + case 24: break; + default: + pr_debug("rejecting bits %d\n", bits); + return -EINVAL; + } + + /* + * channels + */ + dac0 &= ~(3<<6); /* DAC I2S stereo */ + dac1 &= ~(3<<1); /* 2 channels */ + adc1 &= ~(3<<5); /* ADC I2S stereo */ + adc2 &= ~(3<<4); /* 2 channels */ + switch (params_channels(params)) { + case 2: /* I2S stereo mode */ + break; + case 4: /* TDM mode */ + dac0 |= (ad->tdm_mode & 3) << 6; + dac1 |= (1<<1); + adc1 |= (ad->tdm_mode & 3) << 5; + adc2 |= (1<<4); + break; + case 8: /* TDM mode */ + dac0 |= (ad->tdm_mode & 3) << 6; + dac1 |= (2<<1); + adc1 |= (ad->tdm_mode & 3) << 5; + adc2 |= (2<<4); + break; + case 16: /* TDM mode */ + dac0 |= (ad->tdm_mode & 3) << 6; + dac1 |= (3<<1); + adc1 |= (ad->tdm_mode & 3) << 5; + adc2 |= (3<<4); + break; + default: + pr_debug("%d channels not supported\n", + params_channels(params)); + return -EINVAL; + } + + ad1939_write(codec, AD1939_DACCTL0, dac0); + ad1939_write(codec, AD1939_DACCTL1, dac1); + ad1939_write(codec, AD1939_DACCTL2, dac2); + ad1939_write(codec, AD1939_ADCCTL0, adc0); + ad1939_write(codec, AD1939_ADCCTL1, adc1); + ad1939_write(codec, AD1939_ADCCTL2, adc2); + + return 0; +} + +static int ad1939_set_dai_fmt(struct snd_soc_dai *codec_dai, + unsigned int fmt) +{ + struct snd_soc_codec *codec = codec_dai->codec; + unsigned char dac0, dac1, adc1, adc2; + + pr_debug("ad1939_set_dai_fmt(0x%08x)", fmt); + + dac0 = ad1939_read(codec, AD1939_DACCTL0); + dac1 = ad1939_read(codec, AD1939_DACCTL1); + adc1 = ad1939_read(codec, AD1939_ADCCTL1); + adc2 = ad1939_read(codec, AD1939_ADCCTL2); + + /* set master/slave audio interface */ + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + dac1 |= (1<<4) | (1<<5); /* LRCK master, BCK master */ + adc2 |= (1<<3) | (1<<6); /* LRCK master, BCK master */ + break; + case SND_SOC_DAIFMT_CBS_CFM: + dac1 |= (1<<4); /* LRCK master */ + dac1 &= ~(1<<5); /* BCK slave */ + adc2 |= (1<<3); /* LRCK master */ + adc2 &= ~(1<<6); /* BCK slave */ + break; + case SND_SOC_DAIFMT_CBM_CFS: + dac1 &= ~(1<<4); /* LRCK slave */ + dac1 |= (1<<5); /* BCK master */ + adc2 &= ~(1<<3); /* LRCK slave */ + adc2 |= (1<<6); /* BCK master */ + break; + case SND_SOC_DAIFMT_CBS_CFS: + dac1 &= ~((1<<4) | (1<<5)); /* LRCK BCK slave */ + adc2 &= ~((1<<3) | (1<<6)); /* LRCK BCK slave */ + break; + default: + pr_debug("invalid master/slave configuration\n"); + return -EINVAL; + } + + /* interface format */ + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + dac0 &= ~(7<<3); /* DAC: SDATA delay 1 */ + adc1 &= ~(7<<2); /* ADC: SDATA delay 1 */ + break; + case SND_SOC_DAIFMT_MSB: /* LEFT_J */ + dac0 |= (1<<3); /* no SDATA delay */ + adc1 |= (1<<2); /* no SDATA delay */ + break; +#if 0 + case SND_SOC_DAIFMT_LSB: + /* FIXME: need to know if in TDM/Master mode and sample + * size, then program bitdelay accordingly + */ + break; +#endif + default: + pr_err("invalid I2S interface format\n"); + return -EINVAL; + } + + /* clock inversion */ + dac1 &= ~((1<<7) | (1<<3)); /* norm BCK LRCK */ + adc2 &= ~((1<<1) | (1<<2)); /* norm BCK LRCK */ + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + case SND_SOC_DAIFMT_NB_IF: + dac1 |= (1<<3); /* inv LRCK */ + adc2 |= (1<<2); + break; + case SND_SOC_DAIFMT_IB_NF: + dac1 |= (1<<7); /* inv BCK */ + adc2 |= (1<<1); + break; + case SND_SOC_DAIFMT_IB_IF: + dac1 |= (1<<3) | (1<<7); /* inv LRCK BCK */ + adc2 |= (1<<1) | (1<<2); + break; + default: + pr_err("invalid clock inversion configuration\n"); + return -EINVAL; + } + + ad1939_write(codec, AD1939_DACCTL0, dac0); + ad1939_write(codec, AD1939_DACCTL1, dac1); + ad1939_write(codec, AD1939_ADCCTL1, adc1); + ad1939_write(codec, AD1939_ADCCTL2, adc2); + + return 0; +} + +static int ad1939_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level event) +{ + unsigned char pll0, adc0, dac0; + + /* the codec doesn't really have sophisticated PM like the + * WM8731 for example; one can merely turn off DAC, ADC and + * the internal PLL + */ + pll0 = ad1939_read(codec, AD1939_PLLCTL0) & 0xfe; + dac0 = ad1939_read(codec, AD1939_DACCTL0) & 0xfe; + adc0 = ad1939_read(codec, AD1939_ADCCTL0) & 0xfe; + + switch (event) + { + case SND_SOC_BIAS_ON: + case SND_SOC_BIAS_PREPARE: + ad1939_write(codec, AD1939_PLLCTL0, pll0); + ad1939_write(codec, AD1939_DACCTL0, dac0); + ad1939_write(codec, AD1939_ADCCTL0, adc0); + break; + case SND_SOC_BIAS_STANDBY: + case SND_SOC_BIAS_OFF: + /* turn off internal PLL and DAC/ADCs */ + ad1939_write(codec, AD1939_PLLCTL0, pll0 | 1); + ad1939_write(codec, AD1939_DACCTL0, dac0 | 1); + ad1939_write(codec, AD1939_ADCCTL0, adc0 | 1); + break; + } + codec->bias_level = event; + return 0; +} + +static int ad1939_digmute(struct snd_soc_dai *dai, int mute) +{ + dai->codec->write(dai->codec, AD1939_DACMUTE, mute ? 0xff : 0); + return 0; +} + +static int ad1939_set_dai_sysclk(struct snd_soc_dai *codec_dai, + int clk_id, unsigned int freq, int dir) +{ + struct snd_soc_codec *codec = codec_dai->codec; + struct ad1939_private *ad = codec->private_data; + + pr_debug("sysck id %d f %d dir %d\n", clk_id, freq, dir); + switch (freq) { + case 11288000: + ad->sysclk = freq; + break; + default: + pr_err("invalid sysclk\n"); + return -EINVAL; + } + return 0; +} + +#define AD1939_RATES \ + (SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | \ + SNDRV_PCM_RATE_192000) + +#define AD1939_FORMATS \ + (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) + +struct snd_soc_dai ad1939_dai = { + .name = "AD1939", + .playback = { + .stream_name = "Playback", + .channels_min = 2, + .channels_max = 4, /* 4/8 in single/dualline TDM */ + .rates = AD1939_RATES, + .formats = AD1939_FORMATS,}, + .capture = { + .stream_name = "Capture", + .channels_min = 2, + .channels_max = 4, /* yes, 2 DACs! */ + .rates = AD1939_RATES, + .formats = AD1939_FORMATS,}, + .ops = { + .hw_params = ad1939_hw_params, + .digital_mute = ad1939_digmute, + .set_sysclk = ad1939_set_dai_sysclk, + .set_fmt = ad1939_set_dai_fmt, + } +}; +EXPORT_SYMBOL_GPL(ad1939_dai); + + +static int ad1939_init(struct snd_soc_device *socdev) +{ + struct snd_soc_codec *codec = socdev->codec; + struct ad1939_setup_data *setup = socdev->codec_data; + struct ad1939_private *ad = codec->private_data; + unsigned char r0, r1; + int ret; + + codec->owner = THIS_MODULE; + codec->set_bias_level = ad1939_set_bias_level; + codec->dai = &ad1939_dai; + codec->num_dai = 1; + codec->reg_cache_size = ARRAY_SIZE(ad1939_regcache); + codec->reg_cache = kzalloc(sizeof(ad1939_regcache), GFP_KERNEL); + if (!codec->reg_cache) + return -ENOMEM; + + /* "initialize" the codec with default data */ + for (r0 = 0; r0 < AD1939_REGCOUNT; r0++) + ad1939_write(codec, r0, ad1939_regcache[r0]); + + /* + * remember TDM mode and setup clock routing + */ + ad->tdm_mode = setup->tdm_mode; + /* use default TDM mode if noone wants one */ + if ((ad->tdm_mode > AD1939_TDM_MODE_DUALLINE) || (ad->tdm_mode < 1)) + ad->tdm_mode = AD1939_TDM_MODE_TDM; + + r0 = ad1939_read(codec, AD1939_PLLCTL0) & ~(3<<5); + r1 = ad1939_read(codec, AD1939_PLLCTL1) & 3; + + r0 |= (setup->pll_src & 3) << 5; + r0 |= (1<<7); /* enable internal master clock (i.e. the DAC/ADCs) */ + r1 |= setup->dac_adc_clksrc & 3; + ad1939_write(codec, AD1939_PLLCTL0, r0); + ad1939_write(codec, AD1939_PLLCTL1, r1); + + /* Bitclock sources for the ADC and DAC I2S interfaces */ + r0 = ad1939_read(codec, AD1939_DACCTL1); + r1 = ad1939_read(codec, AD1939_ADCCTL2); + r0 &= ~AD1939_BCLKSRC_DAC_PLL; + r1 &= ~AD1939_BCLKSRC_ADC_PLL; + r0 |= setup->dac_adc_clksrc & AD1939_BCLKSRC_DAC_PLL; + r1 |= setup->dac_adc_clksrc & AD1939_BCLKSRC_ADC_PLL; + ad1939_write(codec, AD1939_DACCTL1, r0); + ad1939_write(codec, AD1939_ADCCTL2, r1); + + ad1939_add_controls(codec); + ad1939_set_bias_level(codec, SND_SOC_BIAS_ON); + + ret = snd_soc_init_card(socdev); + if (ret < 0) { + pr_err("failed to register card\n"); + goto card_err; + } + + return 0; + +card_err: + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); + kfree(codec->reg_cache); + return ret; +} + +#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) + +static unsigned short normal_i2c[] = { 0, I2C_CLIENT_END }; + +/* Magic definition of all other variables and things */ +I2C_CLIENT_INSMOD; + +static struct i2c_driver ad1939_i2c_driver; +static struct i2c_client client_template; + +/* If the i2c layer weren't so broken, we could pass this kind of data + around */ +static struct snd_soc_device *ad1939_socdev; + +static int ad1939_codec_probe(struct i2c_adapter *adap, int addr, int kind) +{ + struct snd_soc_device *socdev = ad1939_socdev; + struct snd_soc_codec *codec = socdev->codec; + struct ad1939_setup_data *setup = socdev->codec_data; + struct i2c_client *i2c; + int ret; + + if (addr != setup->i2c_address) + return -ENODEV; + + client_template.adapter = adap; + client_template.addr = addr; + + i2c = kmemdup(&client_template, sizeof(client_template), GFP_KERNEL); + if (i2c == NULL) { + kfree(codec); + return -ENOMEM; + } + i2c_set_clientdata(i2c, codec); + codec->control_data = i2c; + + ret = i2c_attach_client(i2c); + if (ret < 0) { + pr_err("failed to attach codec at addr %x\n", addr); + goto err; + } + + codec->read = ad1939_i2c_read; + codec->write = ad1939_i2c_write; + + ret = ad1939_init(socdev); + if (ret < 0) { + pr_err("failed to initialise AD1939 codec\n"); + goto err; + } + return ret; + +err: + kfree(codec); + kfree(i2c); + return ret; +} + +static int ad1939_i2c_detach(struct i2c_client *client) +{ + struct snd_soc_codec* codec = i2c_get_clientdata(client); + + i2c_detach_client(client); + kfree(codec->reg_cache); + kfree(client); + + return 0; +} + +static int ad1939_i2c_attach(struct i2c_adapter *adap) +{ + return i2c_probe(adap, &addr_data, ad1939_codec_probe); +} + +/* corgi i2c codec control layer */ +static struct i2c_driver ad1939_i2c_driver = { + .driver = { + .name = "AD1939", + .owner = THIS_MODULE, + }, + .id = 103, /* I2C_DRIVERID_AD1939 */ + .attach_adapter = ad1939_i2c_attach, + .detach_client = ad1939_i2c_detach, + .command = NULL, +}; + +static struct i2c_client client_template = { + .name = "AD1939", + .driver = &ad1939_i2c_driver, +}; +#endif /* I2C */ + +static int ad1939_probe(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct ad1939_setup_data *setup; + struct snd_soc_codec *codec; + struct ad1939_private *ad; + int ret; + + ret = -ENOMEM; + setup = socdev->codec_data; + codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); + if (codec == NULL) + goto out; + + ad = kzalloc(sizeof(struct ad1939_private), GFP_KERNEL); + if (ad == NULL) { + kfree(codec); + goto out; + } + ad->codec = codec; + codec->private_data = ad; + socdev->codec = codec; + mutex_init(&codec->mutex); + INIT_LIST_HEAD(&codec->dapm_widgets); + INIT_LIST_HEAD(&codec->dapm_paths); + + ad1939_socdev = socdev; +#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) + if (setup->i2c_address) { + normal_i2c[0] = setup->i2c_address; + ret = i2c_add_driver(&ad1939_i2c_driver); + if (ret != 0) + pr_err("can't add i2c driver"); + } +#endif + ret = 0; +out: + return ret; +} + +static int ad1939_remove(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + + if (codec->control_data) + ad1939_set_bias_level(codec, SND_SOC_BIAS_OFF); + + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); +#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) + i2c_del_driver(&ad1939_i2c_driver); +#endif + kfree(codec->private_data); + kfree(codec); + + return 0; +} + +struct snd_soc_codec_device soc_codec_dev_ad1939 = { + .probe = ad1939_probe, + .remove = ad1939_remove, +}; +EXPORT_SYMBOL_GPL(soc_codec_dev_ad1939); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("ASoC AD1939 I2S Codec driver"); +MODULE_AUTHOR("Manuel Lauss "); diff --git a/sound/soc/codecs/ad1939.h b/sound/soc/codecs/ad1939.h new file mode 100644 index 0000000..464a70a --- /dev/null +++ b/sound/soc/codecs/ad1939.h @@ -0,0 +1,70 @@ +/* + * AD1939 I2S codec + * + */ + +#ifndef _AD1939_H_ +#define _AD1939_H_ + +#define AD1939_PLLCTL0 0x00 +#define AD1939_PLLCTL1 0x01 +#define AD1939_DACCTL0 0x02 +#define AD1939_DACCTL1 0x03 +#define AD1939_DACCTL2 0x04 +#define AD1939_DACMUTE 0x05 +#define AD1939_VOL1L 0x06 +#define AD1939_VOL1R 0x07 +#define AD1939_VOL2L 0x08 +#define AD1939_VOL2R 0x09 +#define AD1939_VOL3L 0x0A +#define AD1939_VOL3R 0x0B +#define AD1939_VOL4L 0x0C +#define AD1939_VOL4R 0x0D +#define AD1939_ADCCTL0 0x0E +#define AD1939_ADCCTL1 0x0F +#define AD1939_ADCCTL2 0x10 + +#define AD1939_REGCOUNT 0x11 + +/* + * AD1939 setup data + */ + +/* TDM modes. Have a look at the manual to understand what these do. */ +#define AD1939_TDM_MODE_TDM 1 +#define AD1939_TDM_MODE_AUX 2 +#define AD1939_TDM_MODE_DUALLINE 3 + +/* Master PLL clock source, select one */ +#define AD1939_PLL_SRC_MCLK 0 /* external clock */ +#define AD1939_PLL_SRC_DACLRCK 1 /* get from DAC LRCLK */ +#define AD1939_PLL_SRC_ADCLRCK 2 /* get from ADC LRCLK */ + +/* clock sources for ADC, DAC. Refer to the manual for more information + * (for 192000kHz modes, internal PLL _MUST_ be used). Select one for ADC + * and DAC. + */ +#define AD1939_CLKSRC_DAC_PLL 0 /* DAC clocked by int. PLL */ +#define AD1939_CLKSRC_DAC_MCLK (1<<0) /* DAC clocked by ext. MCK */ +#define AD1939_CLKSRC_ADC_PLL 0 /* ADC clocked by int. PLL */ +#define AD1939_CLKSRC_ADC_MCLK (1<<1) /* ADC clocked by ext. MCK */ + +/* I2S Bitclock sources for DAC and ADC I2S interfaces. + * OR it to ad1939_setup_data.dac_adc_clksrc. Select one for ADC and DAC. + */ +#define AD1939_BCLKSRC_DAC_EXT 0 /* DAC I2SCLK from DBCLK pin */ +#define AD1939_BCLKSRC_DAC_PLL (1<<6) /* DAC I2SCLK from int. PLL */ +#define AD1939_BCLKSRC_ADC_EXT 0 /* DAC I2SCLK from DBCLK pin */ +#define AD1939_BCLKSRC_ADC_PLL (1<<7) /* DAC I2SCLK from int. PLL */ + +struct ad1939_setup_data { + unsigned char i2c_address; + unsigned char tdm_mode; /* one of AD1939_TDM_MODE_* */ + unsigned char pll_src; /* one of AD1939_PLL_SRC_* */ + unsigned char dac_adc_clksrc; /* AD1939_{B,}CLKSRC_* or'ed together */ +}; + +extern struct snd_soc_codec_device soc_codec_dev_ad1939; +extern struct snd_soc_dai ad1939_dai; + +#endif diff --git a/sound/soc/codecs/ad1980.c b/sound/soc/codecs/ad1980.c index 73fdbb4..c3c5d0e 100644 --- a/sound/soc/codecs/ad1980.c +++ b/sound/soc/codecs/ad1980.c @@ -93,20 +93,6 @@ SOC_ENUM("Capture Source", ad1980_cap_src), SOC_SINGLE("Mic Boost Switch", AC97_MIC, 6, 1, 0), }; -/* add non dapm controls */ -static int ad1980_add_controls(struct snd_soc_codec *codec) -{ - int err, i; - - for (i = 0; i < ARRAY_SIZE(ad1980_snd_ac97_controls); i++) { - err = snd_ctl_add(codec->card, snd_soc_cnew( - &ad1980_snd_ac97_controls[i], codec, NULL)); - if (err < 0) - return err; - } - return 0; -} - static unsigned int ac97_read(struct snd_soc_codec *codec, unsigned int reg) { @@ -269,7 +255,8 @@ static int ad1980_soc_probe(struct platform_device *pdev) ext_status = ac97_read(codec, AC97_EXTENDED_STATUS); ac97_write(codec, AC97_EXTENDED_STATUS, ext_status&~0x3800); - ad1980_add_controls(codec); + snd_soc_add_controls(codec, ad1980_snd_ac97_controls, + ARRAY_SIZE(ad1980_snd_ac97_controls)); ret = snd_soc_init_card(socdev); if (ret < 0) { printk(KERN_ERR "ad1980: failed to register card\n"); diff --git a/sound/soc/codecs/ak4535.c b/sound/soc/codecs/ak4535.c index 81300d8..f17c363 100644 --- a/sound/soc/codecs/ak4535.c +++ b/sound/soc/codecs/ak4535.c @@ -155,21 +155,6 @@ static const struct snd_kcontrol_new ak4535_snd_controls[] = { SOC_SINGLE("Mic Sidetone Volume", AK4535_VOL, 4, 7, 0), }; -/* add non dapm controls */ -static int ak4535_add_controls(struct snd_soc_codec *codec) -{ - int err, i; - - for (i = 0; i < ARRAY_SIZE(ak4535_snd_controls); i++) { - err = snd_ctl_add(codec->card, - snd_soc_cnew(&ak4535_snd_controls[i], codec, NULL)); - if (err < 0) - return err; - } - - return 0; -} - /* Mono 1 Mixer */ static const struct snd_kcontrol_new ak4535_mono1_mixer_controls[] = { SOC_DAPM_SINGLE("Mic Sidetone Switch", AK4535_SIG1, 4, 1, 0), @@ -510,7 +495,8 @@ static int ak4535_init(struct snd_soc_device *socdev) /* power on device */ ak4535_set_bias_level(codec, SND_SOC_BIAS_STANDBY); - ak4535_add_controls(codec); + snd_soc_add_controls(codec, ak4535_snd_controls, + ARRAY_SIZE(ak4535_snd_controls)); ak4535_add_widgets(codec); ret = snd_soc_init_card(socdev); if (ret < 0) { diff --git a/sound/soc/codecs/cs4251x.c b/sound/soc/codecs/cs4251x.c new file mode 100644 index 0000000..867e8f3 --- /dev/null +++ b/sound/soc/codecs/cs4251x.c @@ -0,0 +1,755 @@ +/* + * cs4251x.h -- Cirrus/Crystal CS42516/42518 I2C Codec Soc Audio driver + * + * Copyright 2007 MSC Vertriebsges.m.b.h, + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * The CS4251X is quite complex; please have a look at the manual before + * using it: http:///www.cirrus.com/en/pubs/proDatasheet/CS42518_F1.pdf + */ + +/* + * FIXME: A LOT of this code assumes that the CODEC_SP interface is used + * for playback and the SAI_SP for recording (because this is the + * configuration I'm working with). Look at the hw_params + * function for example (setting the Fs ratio based on OMCK) + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cs4251x.h" + +#define AUDIO_NAME "cs4251x" + +/* codec private data */ +struct cs_priv { + struct snd_soc_codec *codec; + struct work_struct irq_work; + unsigned long sysclk; + int irq; +}; + +#define FS_RATIO_CNT 3 +/* oversampling clock ratios. + * OMCK/ratio = samplerate. + */ +static const unsigned int cs_fs_ratios[FS_RATIO_CNT] = { + 512, 256, 128 +}; + +/* codec register values after reset */ +static const u16 cs4251x_regcache[CS4251X_REGNUM] __devinitdata = { + 0x00, 0xE3, 0x81, 0x00, 0x40, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x09, 0x09, 0x09, 0x09, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, + 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, +}; + +/* + * write to the cs4251x register space + */ +static int cs_i2c_write(struct snd_soc_codec *codec, unsigned int reg, + unsigned int value) +{ + struct i2c_msg msg; + struct i2c_client *c; + u16 *cache = codec->reg_cache; + u8 data[2]; + int ret; + + reg &= 0x7f; /* kill the auto-addr-increment bit */ + + /* exclude read-only regs */ + switch (reg) { + case 0 ... 1: + case 0x07 ... 0x0c: + case 0x20: + case 0x25: + case 0x26: + case 0x30 ... 0x51: + return 0; + } + + if (value == cache[reg]) + return 0; + + c = (struct i2c_client *)codec->control_data; + data[0] = reg & 0xff; + data[1] = value & 0xff; + msg.addr = c->addr; + msg.flags = 0; /* write */ + msg.buf = &data[0]; + msg.len = 2; + + ret = i2c_transfer(c->adapter, &msg, 1); + if (ret == 1) + cache[reg] = value; + return (ret == 1) ? 0 : -EIO; +} + +static unsigned int cs_i2c_read(struct snd_soc_codec *codec, + unsigned int reg) +{ + struct i2c_msg msg[2]; + struct i2c_client *c; + u8 data[2]; + u16 *cache = codec->reg_cache; + int ret; + + /* check for the uncachables */ + switch (reg) { + case 1: + case 0x07 ... 0x0c: + case 0x20: + case 0x25: + case 0x26: + case 0x30 ... 0x51: + break; + default: + return cache[reg]; + } + + c = (struct i2c_client *)codec->control_data; + data[0] = reg & 0xff; + msg[0].addr = c->addr; + msg[0].flags = 0; + msg[0].buf = &data[0]; + msg[0].len = 1; + + msg[1].addr = c->addr; + msg[1].flags = I2C_M_RD; + msg[1].buf = &data[1]; + msg[1].len = 1; + + ret = i2c_transfer(c->adapter, &msg[0], 2); + return (ret == 2) ? data[1] : -EIO; +} + +int cs4251x_write(struct snd_soc_codec *codec, unsigned int reg, + unsigned int value) +{ + return codec->write(codec, reg, value); +} +EXPORT_SYMBOL_GPL(cs4251x_write); + +unsigned int cs4251x_read(struct snd_soc_codec *codec, unsigned int reg) +{ + return codec->read(codec, reg); +} +EXPORT_SYMBOL_GPL(cs4251x_read); + +/** + * cs4251x_gpio_set - set gpio output level (high/low) + * @codec: snd_soc_codec structure for this codec. + * @gpio: index of GPIO pin to set (0-6). + * @val: 0 for low-leve, 1 for high-level. + */ +void cs4251x_gpio_set(struct snd_soc_codec *codec, unsigned char gpio, + unsigned char val) +{ + unsigned char v; + + if (gpio > 6) + return; + + v = cs4251x_read(codec, CS4251X_GPIO_0 + gpio); + v &= 0x3f; + if (val) + v |= 3 << 6; /* GPO, high level */ + else + v |= 2 << 6; /* GPO, low level */ + cs4251x_write(codec, CS4251X_GPIO_0 + gpio, v); +} +EXPORT_SYMBOL_GPL(cs4251x_gpio_set); + +/** + * cs4251x_gpio_mode - set gpio/rxp pin mode. + * @codec: snd_soc_codec structure for this codec. + * @gpio: index of GPIO pin to set (0-6). + * @val: see GPIO_MODE_xxx constants. + */ +void cs4251x_gpio_mode(struct snd_soc_codec *codec, unsigned char gpio, + unsigned char mode, unsigned char polarity, + unsigned char funcmode) +{ + unsigned char v; + + if (unlikely(gpio > 6)) + return; + + switch (mode) + { + case CS4251X_GPIO_MODE_RXP: v = (0 << 6); break; + case CS4251X_GPIO_MODE_GPOHI: v = (3 << 6); break; + case CS4251X_GPIO_MODE_GPOLOW: + v = (2 << 6) | (funcmode & 1) | ((funcmode & 1) << 1); + break; + case CS4251X_GPIO_MODE_MUTE: + v = (1 << 6) | ((polarity & 1) << 5) | + (funcmode & CS4251X_FUNCMODE_MUTE_MASK); + break; + default: + return; + } + cs4251x_write(codec, CS4251X_GPIO_0 + gpio, v); +} +EXPORT_SYMBOL_GPL(cs4251x_gpio_mode); + +static void cs_irq_work(struct work_struct *data) +{ + struct cs_priv *cs = + container_of(data, struct cs_priv, irq_work); + unsigned char r; + + r = cs4251x_read(cs->codec, CS4251X_IRQSTAT); + pr_debug("IRQ: istat 0x%02x", r); +} + +static irqreturn_t cs_irq(int irq, void *dev_id) +{ + struct cs_priv *cs = dev_id; + schedule_work(&cs->irq_work); + return IRQ_HANDLED; +} + +static const char *cs_vol_transition[] = { + "Immediate", "Zero-Cross", "Soft-Ramp", + "Soft-Ramp on Zero-Crossings" +}; +static const char *cs_off_on[] = {"Off", "On"}; + +static const struct soc_enum cs_enum[] = { + /*SOC_ENUM_SINGLE(reg, startbit, choicecount, choices-texts), */ + SOC_ENUM_SINGLE(CS4251X_VOLTRANSCTL, 4, 4, cs_vol_transition), + SOC_ENUM_SINGLE(CS4251X_VOLTRANSCTL, 6, 2, cs_off_on), + SOC_ENUM_SINGLE(CS4251X_VOLTRANSCTL, 3, 2, cs_off_on), + SOC_ENUM_SINGLE(CS4251X_VOLTRANSCTL, 1, 2, cs_off_on), + SOC_ENUM_SINGLE(CS4251X_VOLTRANSCTL, 0, 2, cs_off_on), + SOC_ENUM_SINGLE(CS4251X_FUNCMODE, 1, 2, cs_off_on), + SOC_ENUM_SINGLE(CS4251X_FUNCMODE, 0, 2, cs_off_on), +}; + +static const struct snd_kcontrol_new cs_snd_controls[] = { +SOC_DOUBLE_R("Master Playback Volume", CS4251X_L1VOL, CS4251X_R1VOL, 0, 255, 1), +SOC_DOUBLE_R("Channel 2 Playback Volume", CS4251X_L2VOL, CS4251X_R2VOL, 0, 255, 1), +SOC_DOUBLE_R("Channel 3 Playback Volume", CS4251X_L3VOL, CS4251X_R3VOL, 0, 255, 1), +SOC_DOUBLE_R("Channel 4 Playback Volume", CS4251X_L4VOL, CS4251X_R4VOL, 0, 255, 1), + +SOC_DOUBLE_R("Capture Volume", CS4251X_LADCGAIN, CS4251X_RADCGAIN, 0, 255, 0), + +SOC_ENUM("Volume Transition", cs_enum[0]), +SOC_ENUM("Soft Volume Ramp-Up after Error", cs_enum[3]), +SOC_ENUM("Soft Volume Ramp-Down before Filter Change", cs_enum[4]), +SOC_ENUM("DAC Auto-Mute", cs_enum[2]), +SOC_ENUM("DAC Deemphasis", cs_enum[5]), +SOC_ENUM("Receiver Deemphasis", cs_enum[6]), + +}; + +/* add non dapm controls */ +static int cs_add_controls(struct snd_soc_codec *codec) +{ + int err, i; + + for (i = 0; i < ARRAY_SIZE(cs_snd_controls); i++) { + err = snd_ctl_add(codec->card, + snd_soc_cnew(&cs_snd_controls[i], codec, NULL)); + + if (err < 0) + return err; + } + + return 0; +} + +static int cs_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->codec; + struct cs_priv *cs = codec->private_data; + unsigned long rate; + unsigned char funcmode; + int i; + + pr_debug("cs_hw_params"); + + rate = params->rate_num / params->rate_den; + for (i = 0; i < FS_RATIO_CNT; i++) { + + pr_debug("%d sck %lu rat %d res %lu rate %lu", i, cs->sysclk, + cs_fs_ratios[i], + (cs->sysclk / cs_fs_ratios[i]), rate); + + if ((cs->sysclk / cs_fs_ratios[i]) == rate) { + /* found a suitable ratio, program it */ + funcmode = cs4251x_read(codec, CS4251X_FUNCMODE); + /* set both CODEC_SP and SAI_SP */ + pr_debug("funcmode: was %x", funcmode); + funcmode &= ~(15<<4); + funcmode |= (i<<4) | (i<<6); + pr_debug("funcmode: is now %x", funcmode); + cs4251x_write(codec, CS4251X_FUNCMODE, funcmode); + return 0; + } + } + /* eek, nothing suitable found */ + return -EINVAL; +} + +static int cs_mute(struct snd_soc_dai *dai, int mute) +{ + cs4251x_write(dai->codec, CS4251X_MUTE, mute ? 0xff : 0); + return 0; +} + +/* + * someone wants to tell us the OMCK frequency we're running with. + */ +static int cs_set_dai_sysclk(struct snd_soc_dai *codec_dai, + int clk_id, unsigned int freq, int dir) +{ + struct snd_soc_codec *codec = codec_dai->codec; + struct cs_priv *cs = codec->private_data; + unsigned char ckctl; + unsigned long rates; + + pr_debug("cs_set_dai_sysclk(%d, %ul, %d)", clk_id, freq, dir); + + ckctl = cs4251x_read(codec, CS4251X_CLKCTL); + ckctl &= ~(3<<4); + + /* NOTE: these clock rates come from the datasheet... */ + switch (freq) { + case 11289600: + rates = SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | + SNDRV_PCM_RATE_88200; + break; + case 12288000: + rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000; + break; + case 16934400: + case 18432000: + /* well, none that ALSA has #defines for: + * 33075Hz, 66150Hz, 132300Hz, 36, 72, 144kHz + */ + rates = 0; + ckctl |= (1<<4); + break; + case 22579200: + rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 | + SNDRV_PCM_RATE_176400; + ckctl |= (2<<4); + break; + case 24576000: + rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | + SNDRV_PCM_RATE_192000; + ckctl |= (2<<4); + break; + default: + pr_debug("invalid sysclk %uHz", freq); + return -EINVAL; + } + + /* tell the codec about the new OMCK range */ + cs4251x_write(codec, CS4251X_CLKCTL, ckctl); + cs->sysclk = freq; /* need to know in hw_params */ + +#if 0 /* does not work, boooooooo */ + /* update the DAI's supported rates mask */ + codec_dai->playback.rates = rates; + codec_dai->capture.rates = rates; +#endif + return 0; +} + +/* + * set Interface Format. + * FIXME: this code applies the same values to the CODEC_SP and SAI_SP + * interfaces, although technically they're independent. + */ +static int cs_set_dai_fmt(struct snd_soc_dai *codec_dai, + unsigned int fmt) +{ + struct snd_soc_codec *codec = codec_dai->codec; + u8 iffmt, misc; + + pr_debug("cs_set_dai_fmt(0x%08x)", fmt); + + iffmt = cs4251x_read(codec, CS4251X_IFFMT); + misc = cs4251x_read(codec, CS4251X_MISCCTL); + + /* set master/slave audio interface */ + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + misc |= 3; /* CODEC_SP and SAI in master mode */ + break; + case SND_SOC_DAIFMT_CBS_CFS: + misc &= ~2; /* CODEC_SP_and SAI in slave mode */ + break; + default: + return -EINVAL; + } + + /* interface format */ + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + iffmt &= ~0xc0; + iffmt |= 1 << 6; + break; + case SND_SOC_DAIFMT_RIGHT_J: + iffmt &= ~0xc0; + iffmt |= 1 << 7; + break; + case SND_SOC_DAIFMT_LEFT_J: + iffmt &= ~0xc0; + break; + default: + return -EINVAL; + } + + /* clock inversion */ + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + default: + return -EINVAL; + } + + /* set iface */ + cs4251x_write(codec, CS4251X_IFFMT, iffmt); + cs4251x_write(codec, CS4251X_MISCCTL, misc); + + return 0; +} + +static int cs_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level event) +{ + switch (event) + { + case SND_SOC_BIAS_ON: + case SND_SOC_BIAS_PREPARE: + cs4251x_write(codec, CS4251X_PM, 0); + break; + case SND_SOC_BIAS_STANDBY: + case SND_SOC_BIAS_OFF: + /* all DAC/ADCs off, power down */ + cs4251x_write(codec, CS4251X_PM, 0xff); + break; + } + codec->bias_level = event; + return 0; +} + +/* FIXME: really depends on sysclk! */ +#define CS4251X_RATES \ + (SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | \ + SNDRV_PCM_RATE_192000) + +#define CS4251X_FORMATS \ + (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) + +/* + * This is slightly incorrect: The codec has 4 CODEC_SP interfaces (each + * connected to a DAC; 1st also connected to ADCs) and 1 SAI_SP interface + * (connected to ADC and SPDIF receiver). The 4 CODEC_SP and the SAI_SP + * can be configured independently. + */ +struct snd_soc_dai cs4251x_dai = { + .name = "CS4251x", + .playback = { + .stream_name = "Playback", + .channels_min = 1, + .channels_max = 2, + .rates = CS4251X_RATES, /* depends on clock source */ + .formats = CS4251X_FORMATS,}, + .capture = { + .stream_name = "Capture", + .channels_min = 1, + .channels_max = 2, + .rates = CS4251X_RATES, + .formats = CS4251X_FORMATS,}, + .ops = { + .hw_params = cs_hw_params, + .digital_mute = cs_mute, + .set_sysclk = cs_set_dai_sysclk, + .set_fmt = cs_set_dai_fmt, + } +}; +EXPORT_SYMBOL_GPL(cs4251x_dai); + +/* + * initialise the cs42516/8/28 codec. + * register the mixer and dsp interfaces with the kernel + */ +static int cs_init(struct snd_soc_device *socdev) +{ + struct snd_soc_codec *codec = socdev->codec; + struct cs_priv *cs = codec->private_data; + struct cs4251x_setup_data *setup = socdev->codec_data; + int reg, ret; + + codec->owner = THIS_MODULE; + codec->set_bias_level = cs_bias_level; + codec->dai = &cs4251x_dai; + codec->num_dai = 1; + codec->reg_cache_size = ARRAY_SIZE(cs4251x_regcache); + codec->reg_cache = kzalloc(sizeof(cs4251x_regcache), GFP_KERNEL); + if (!codec->reg_cache) + return -ENOMEM; + + ret = -ENODEV; + /* init the chip, populate regcache */ + for (reg = 1; reg < CS4251X_REGNUM; reg++) + cs4251x_write(codec, reg, cs4251x_regcache[reg]); + + /* identify the chip */ + reg = cs4251x_read(codec, CS4251X_CHIPID); + if (unlikely(reg < 0)) + goto pcm_err; + + switch (reg & 0xf0) + { + case 0xe0: + codec->name = "CS42518"; + break; + case 0xf0: + codec->name = "CS42516/CS42528"; + break; + default: + pr_info("unknown chip-id %02x; skipping", reg); + goto pcm_err; + } + + /* Hello, World! */ + printk(KERN_INFO "%s Rev. %c I2S Audio Codec\n", + codec->name, 'A' - 1 + (reg & 15)); + + /* register pcms */ + ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, + SNDRV_DEFAULT_STR1); + if (unlikely(ret < 0)) { + pr_err("failed to create pcms"); + goto pcm_err; + } + + cs_add_controls(codec); + cs_bias_level(codec, SND_SOC_BIAS_STANDBY); + + ret = snd_soc_init_card(socdev); + if (unlikely(ret < 0)) { + pr_err("failed to register card\n"); + goto card_err; + } + + cs->irq = setup->irq; + if (cs->irq != CS4251X_NOIRQ) { + INIT_WORK(&cs->irq_work, cs_irq_work); + reg = request_irq(cs->irq, cs_irq, 0, "cs4251x", cs); + if (unlikely(reg)) { + pr_info("irq attach failed"); + cs->irq = CS4251X_NOIRQ; + } + } + + return 0; + +card_err: + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); +pcm_err: + kfree(codec->reg_cache); + return ret; +} + +#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) +static unsigned short normal_i2c[] = { 0, I2C_CLIENT_END }; + +/* Magic definition of all other variables and things */ +I2C_CLIENT_INSMOD; + +static struct i2c_driver cs_i2c_driver; +static struct i2c_client client_template; + +/* If the i2c layer weren't so broken, we could pass this kind of data + around */ +static struct snd_soc_device *cs_socdev; + +static int cs_codec_probe(struct i2c_adapter *adap, int addr, int kind) +{ + struct snd_soc_device *socdev = cs_socdev; + struct snd_soc_codec *codec = socdev->codec; + struct cs4251x_setup_data *setup = socdev->codec_data; + struct i2c_client *i2c; + int ret; + + if (addr != setup->i2c_address) + return -ENODEV; + + client_template.adapter = adap; + client_template.addr = addr; + + i2c = kmemdup(&client_template, sizeof(client_template), GFP_KERNEL); + if (unlikely(i2c == NULL)) { + kfree(codec); + return -ENOMEM; + } + i2c_set_clientdata(i2c, codec); + codec->control_data = i2c; + + ret = i2c_attach_client(i2c); + if (unlikely(ret < 0)) { + pr_err("failed to attach codec at addr %x", addr); + goto err; + } + + codec->read = cs_i2c_read; + codec->write = cs_i2c_write; + + ret = cs_init(socdev); + if (unlikely(ret < 0)) { + pr_err("failed to initialise CS4251x"); + goto err; + } + return ret; + +err: + kfree(codec); + kfree(i2c); + return ret; +} + +static int cs_i2c_detach(struct i2c_client *client) +{ + struct snd_soc_codec *codec = i2c_get_clientdata(client); + struct cs_priv *cs = codec->private_data; + + if (cs->irq != CS4251X_NOIRQ) { + free_irq(cs->irq, cs); + flush_scheduled_work(); + } + + i2c_detach_client(client); + kfree(codec->reg_cache); + kfree(client); + + return 0; +} + +static int cs_i2c_attach(struct i2c_adapter *adap) +{ + return i2c_probe(adap, &addr_data, cs_codec_probe); +} + +static struct i2c_driver cs_i2c_driver = { + .driver = { + .name = "cs4251x", + .owner = THIS_MODULE, + }, + .id = 102, /* I2C_DRIVERID_CS4251X */ + .attach_adapter = cs_i2c_attach, + .detach_client = cs_i2c_detach, +}; + +static struct i2c_client client_template = { + .name = "CS425XX", + .driver = &cs_i2c_driver, +}; +#endif + +static int cs_probe(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct cs4251x_setup_data *setup = socdev->codec_data; + struct snd_soc_codec *codec; + struct cs_priv *cs; + int ret; + + ret = -ENOMEM; + codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); + if (codec == NULL) + goto out; + + cs = kzalloc(sizeof(struct cs_priv), GFP_KERNEL); + if (cs == NULL) { + kfree(codec); + goto out; + } + ret = 0; + + cs->codec = codec; + codec->private_data = cs; + socdev->codec = codec; + mutex_init(&codec->mutex); + INIT_LIST_HEAD(&codec->dapm_widgets); + INIT_LIST_HEAD(&codec->dapm_paths); + cs_socdev = socdev; +#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) + if (setup->i2c_address) { + normal_i2c[0] = setup->i2c_address; + ret = i2c_add_driver(&cs_i2c_driver); + if (ret) + pr_err("can't add i2c driver"); + } +#endif + +out: + return ret; +} + +/* power down chip */ +static int cs_remove(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + + if (codec->control_data) + cs_bias_level(codec, SND_SOC_BIAS_OFF); + + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); +#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) + i2c_del_driver(&cs_i2c_driver); +#endif + kfree(codec->private_data); + kfree(codec); + + return 0; +} + +struct snd_soc_codec_device soc_codec_dev_cs4251x = { + .probe = cs_probe, + .remove = cs_remove, +}; +EXPORT_SYMBOL_GPL(soc_codec_dev_cs4251x); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("ASoC CS42516/42518 I2S codec driver"); +MODULE_AUTHOR("Manuel Lauss "); diff --git a/sound/soc/codecs/cs4251x.h b/sound/soc/codecs/cs4251x.h new file mode 100644 index 0000000..9f52038 --- /dev/null +++ b/sound/soc/codecs/cs4251x.h @@ -0,0 +1,174 @@ +/* + * cs4251x.h -- Cirrus/Crystal CS42516/42518 I2C Codec Soc Audio driver + * + * Copyright 2007 MSC Vertriebsges.m.b.h, + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * The CS4251X is quite complex; please have a look at the manual before + * using it: http:///www.cirrus.com/en/pubs/proDatasheet/CS42518_F1.pdf + * + */ + +#ifndef _CS4251X_H +#define _CS4251X_H + +struct cs4251x_setup_data { + unsigned short i2c_address; + unsigned int irq; /* yeah, the CS4251X has an IRQ line! */ +}; + +#define CS4251X_NOIRQ (-1) + +/* + * Codec clock control + * see manual pages 53-54, chapter 6.7 + */ + +/* always use OMCK clock */ +#define CS4251X_CLKSRC_OMCK (0 << 1) +/* always use PLL recovered clk */ +#define CS4251X_CLKSRC_PLL (1 << 1) +/* keep current; on unlock stay with OMCK forever */ +#define CS4251X_CLKSRC_CURRENT_OMCK (2 << 1) +/* use PLL when locked, otherwise OMCK */ +#define CS4251X_CLKSRC_AUTO_PLL_OMCK (3 << 1) +#define CS4251X_CLKSRC_MCK_MASK (3 << 1) + +/* PLL input is SPDIF receiver */ +#define CS4251X_CLKSRC_PLL_SPDIF 0 +/* PLL input is SAI_LRCLK */ +#define CS4251X_CLKSRC_PLL_LRCLK (1 << 2) + +/* force lock on PLL. CLKSRC_OMCK MUST be used! */ +#define CS4251X_CLKSRC_PLL_FORCE_LOCK (1 << 0) + +#define CS4251X_CLKSRC_RMCK_DIV_1 (0 << 7) +#define CS4251X_CLKSRC_RMCK_DIV_2 (1 << 7) +#define CS4251X_CLKSRC_RMCK_DIV_4 (2 << 7) +#define CS4251X_CLKSRC_RMCK_MUL_2 (3 << 7) + +#define CS4251X_CLKSRC_OMCK_112896MHZ (0 << 4) +#define CS4251X_CLKSRC_OMCK_122880MHZ (0 << 4) +#define CS4251X_CLKSRC_OMCK_169344MHZ (1 << 4) +#define CS4251X_CLKSRC_OMCK_184320MHZ (1 << 4) +#define CS4251X_CLKSRC_OMCK_225792MHZ (2 << 4) +#define CS4251X_CLKSRC_OMCK_245760MHZ (2 << 4) +#define CS4251X_CLKSRC_OMCK_FMASK (3 << 4) + +/* + * ADC serial interface flags + * See manual page 49, (ch 6.4.3) + */ +/* ADC data on CX_SDOUT, clock provided by CODEC_SP, + * SPDIF data on SAI_SDOUT + */ +#define CS4251X_ADCDAI_CXSDOUT_CODECSP_CLK (0 << 2) +/* ADC data on CX_SDOUT, clock provided by SAI_SP. + * SPDIF data on SAI_SDOUT + */ +#define CS4251X_ADCDAI_CXSDOUT_SAISP_CLK (1 << 2) +/* ADC data on SAI_SDOUT, clock provided by SAI_SP. + * No SPDIF data + */ +#define CS4251X_ADCDAI_SAISDOUT_SAISP_CLK (2 << 2) + +/** miscctl flags */ +/* SAI interface is I2S master/slave */ +#define CS4251X_MISC_SAISP_MASTER (1 << 0) +#define CS4251X_MISC_SAISP_SLAVE 0 +/* CODEC_SP interface is I2S master/slave */ +#define CS4251X_MISC_CODECSP_MASTER (1 << 1) +#define CS4251X_MISC_CODECSP_SLAVE 0 + +#define CS4251X_MISC_HIGHPASS_FREEZE (1 << 2) + +#define CS4251X_MISC_DAC_FAST_ROLLOFF (1 << 3) +#define CS4251X_MISC_DAC_SLOW_ROLLOFF 0 + +#define CS4251X_MISC_RMCK_HIGHZ (1 << 6) + +/** CS4251X internal registers **/ + +/* register 0 does not exist */ +#define CS4251X_CHIPID 0x01 +#define CS4251X_PM 0x02 +#define CS4251X_FUNCMODE 0x03 +#define CS4251X_IFFMT 0x04 +#define CS4251X_MISCCTL 0x05 +#define CS4251X_CLKCTL 0x06 +#define CS4251X_PLLOMCKRATIO 0x07 +#define CS4251X_RCVSTAT 0x08 +#define CS4251X_VOLTRANSCTL 0x0D +#define CS4251X_MUTE 0x0E +#define CS4251X_L1VOL 0x0F +#define CS4251X_R1VOL 0x10 +#define CS4251X_L2VOL 0x11 +#define CS4251X_R2VOL 0x12 +#define CS4251X_L3VOL 0x13 +#define CS4251X_R3VOL 0x14 +#define CS4251X_L4VOL 0x15 +#define CS4251X_R4VOL 0x16 +#define CS4251X_LADCGAIN 0x1C +#define CS4251X_RADCGAIN 0x1D +#define CS4251X_RCVMODECTL 0x1E +#define CS4251X_RCVMODECTL2 0x1F +#define CS4251X_IRQSTAT 0x20 +#define CS4251X_IRQMASK 0x21 +#define CS4251X_MUTEC 0x28 +#define CS4251X_GPIO_0 0x29 +/* there are more, but irrelevant for now ;-) */ +#define CS4251X_REGNUM 0x52 + +/* + * GPIO control + */ +#define CS4251X_RXP_0 7 +#define CS4251X_RXP_1 6 +#define CS4251X_RXP_2 5 +#define CS4251X_RXP_3 4 +#define CS4251X_RXP_4 3 +#define CS4251X_RXP_5 2 +#define CS4251X_RXP_6 1 +#define CS4251X_RXP_7 0 + +#define CS4251X_GPIO_MODE_RXP 0 +#define CS4251X_GPIO_MODE_MUTE 1 +#define CS4251X_GPIO_MODE_GPOLOW 2 +#define CS4251X_GPIO_MODE_GPOHI 3 + +#define CS4251X_GPIO_MUTEPOL_LOW 0 +#define CS4251X_GPIO_MUTEPOL_HIGH 1 + +/* just use as low-level GPO */ +#define CS4251X_FUNCMODE_GPO_DRIVELOW 0 +/* pin indicates ADC overflow */ +#define CS4251X_FUNCMODE_GPO_OVERFLOW 1 + +/* in mutemode, a bitmask determines which DACs are muted by which RXP + * pins. Please have a look at CS42518_PP5.pdf datasheet, page 71 for + * the matrix */ +#define CS4251X_FUNCMODE_MUTE_MASK 0x1f + +void cs4251x_gpio_set(struct snd_soc_codec *codec, unsigned char gpio, + unsigned char val); +void cs4251x_gpio_mode(struct snd_soc_codec *codec, unsigned char gpio, + unsigned char mode, unsigned char polarity, + unsigned char funcmode); + +/* + * access to the codec registers + */ +int cs4251x_write(struct snd_soc_codec *codec, unsigned int reg, + unsigned int value); + +unsigned int cs4251x_read(struct snd_soc_codec *codec, unsigned int reg); + + +/* ASoC DAI */ +extern struct snd_soc_dai cs4251x_dai; +extern struct snd_soc_codec_device soc_codec_dev_cs4251x; + +#endif diff --git a/sound/soc/codecs/ssm2602.c b/sound/soc/codecs/ssm2602.c index cac3736..ec7fe3b 100644 --- a/sound/soc/codecs/ssm2602.c +++ b/sound/soc/codecs/ssm2602.c @@ -151,21 +151,6 @@ SOC_ENUM("Capture Source", ssm2602_enum[0]), SOC_ENUM("Playback De-emphasis", ssm2602_enum[1]), }; -/* add non dapm controls */ -static int ssm2602_add_controls(struct snd_soc_codec *codec) -{ - int err, i; - - for (i = 0; i < ARRAY_SIZE(ssm2602_snd_controls); i++) { - err = snd_ctl_add(codec->card, - snd_soc_cnew(&ssm2602_snd_controls[i], codec, NULL)); - if (err < 0) - return err; - } - - return 0; -} - /* Output Mixer */ static const struct snd_kcontrol_new ssm2602_output_mixer_controls[] = { SOC_DAPM_SINGLE("Line Bypass Switch", SSM2602_APANA, 3, 1, 0), @@ -622,7 +607,8 @@ static int ssm2602_init(struct snd_soc_device *socdev) APANA_ENABLE_MIC_BOOST); ssm2602_write(codec, SSM2602_PWR, 0); - ssm2602_add_controls(codec); + snd_soc_add_controls(codec, ssm2602_snd_controls, + ARRAY_SIZE(ssm2602_snd_controls)); ssm2602_add_widgets(codec); ret = snd_soc_init_card(socdev); if (ret < 0) { diff --git a/sound/soc/codecs/tlv320aic23.c b/sound/soc/codecs/tlv320aic23.c index cfdea00..a0e47c1 100644 --- a/sound/soc/codecs/tlv320aic23.c +++ b/sound/soc/codecs/tlv320aic23.c @@ -183,24 +183,6 @@ static const struct snd_kcontrol_new tlv320aic23_snd_controls[] = { SOC_ENUM("Playback De-emphasis", tlv320aic23_deemph), }; -/* add non dapm controls */ -static int tlv320aic23_add_controls(struct snd_soc_codec *codec) -{ - - int err, i; - - for (i = 0; i < ARRAY_SIZE(tlv320aic23_snd_controls); i++) { - err = snd_ctl_add(codec->card, - snd_soc_cnew(&tlv320aic23_snd_controls[i], - codec, NULL)); - if (err < 0) - return err; - } - - return 0; - -} - /* PGA Mixer controls for Line and Mic switch */ static const struct snd_kcontrol_new tlv320aic23_output_mixer_controls[] = { SOC_DAPM_SINGLE("Line Bypass Switch", TLV320AIC23_ANLG, 3, 1, 0), @@ -718,7 +700,8 @@ static int tlv320aic23_init(struct snd_soc_device *socdev) tlv320aic23_write(codec, TLV320AIC23_ACTIVE, 0x1); - tlv320aic23_add_controls(codec); + snd_soc_add_controls(codec, tlv320aic23_snd_controls, + ARRAY_SIZE(tlv320aic23_snd_controls)); tlv320aic23_add_widgets(codec); ret = snd_soc_init_card(socdev); if (ret < 0) { diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c index aea0cb7..e66772d 100644 --- a/sound/soc/codecs/tlv320aic3x.c +++ b/sound/soc/codecs/tlv320aic3x.c @@ -314,22 +314,6 @@ static const struct snd_kcontrol_new aic3x_snd_controls[] = { SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]), }; -/* add non dapm controls */ -static int aic3x_add_controls(struct snd_soc_codec *codec) -{ - int err, i; - - for (i = 0; i < ARRAY_SIZE(aic3x_snd_controls); i++) { - err = snd_ctl_add(codec->card, - snd_soc_cnew(&aic3x_snd_controls[i], - codec, NULL)); - if (err < 0) - return err; - } - - return 0; -} - /* Left DAC Mux */ static const struct snd_kcontrol_new aic3x_left_dac_mux_controls = SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]); @@ -1227,7 +1211,8 @@ static int aic3x_init(struct snd_soc_device *socdev) aic3x_write(codec, AIC3X_GPIO1_REG, (setup->gpio_func[0] & 0xf) << 4); aic3x_write(codec, AIC3X_GPIO2_REG, (setup->gpio_func[1] & 0xf) << 4); - aic3x_add_controls(codec); + snd_soc_add_controls(codec, aic3x_snd_controls, + ARRAY_SIZE(aic3x_snd_controls)); aic3x_add_widgets(codec); ret = snd_soc_init_card(socdev); if (ret < 0) { diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c index ea370a4..ddc9f37 100644 --- a/sound/soc/codecs/twl4030.c +++ b/sound/soc/codecs/twl4030.c @@ -670,22 +670,6 @@ static const struct snd_kcontrol_new twl4030_snd_controls[] = { 0, 3, 5, 0, input_gain_tlv), }; -/* add non dapm controls */ -static int twl4030_add_controls(struct snd_soc_codec *codec) -{ - int err, i; - - for (i = 0; i < ARRAY_SIZE(twl4030_snd_controls); i++) { - err = snd_ctl_add(codec->card, - snd_soc_cnew(&twl4030_snd_controls[i], - codec, NULL)); - if (err < 0) - return err; - } - - return 0; -} - static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = { /* Left channel inputs */ SND_SOC_DAPM_INPUT("MAINMIC"), @@ -1233,7 +1217,8 @@ static int twl4030_init(struct snd_soc_device *socdev) /* power on device */ twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY); - twl4030_add_controls(codec); + snd_soc_add_controls(codec, twl4030_snd_controls, + ARRAY_SIZE(twl4030_snd_controls)); twl4030_add_widgets(codec); ret = snd_soc_init_card(socdev); diff --git a/sound/soc/codecs/uda134x.c b/sound/soc/codecs/uda134x.c index a2c5064..277825d 100644 --- a/sound/soc/codecs/uda134x.c +++ b/sound/soc/codecs/uda134x.c @@ -431,39 +431,6 @@ SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]), SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0), }; -static int uda134x_add_controls(struct snd_soc_codec *codec) -{ - int err, i, n; - const struct snd_kcontrol_new *ctrls; - struct uda134x_platform_data *pd = codec->control_data; - - switch (pd->model) { - case UDA134X_UDA1340: - case UDA134X_UDA1344: - n = ARRAY_SIZE(uda1340_snd_controls); - ctrls = uda1340_snd_controls; - break; - case UDA134X_UDA1341: - n = ARRAY_SIZE(uda1341_snd_controls); - ctrls = uda1341_snd_controls; - break; - default: - printk(KERN_ERR "%s unkown codec type: %d", - __func__, pd->model); - return -EINVAL; - } - - for (i = 0; i < n; i++) { - err = snd_ctl_add(codec->card, - snd_soc_cnew(&ctrls[i], - codec, NULL)); - if (err < 0) - return err; - } - - return 0; -} - struct snd_soc_dai uda134x_dai = { .name = "UDA134X", /* playback capabilities */ @@ -572,7 +539,22 @@ static int uda134x_soc_probe(struct platform_device *pdev) goto pcm_err; } - ret = uda134x_add_controls(codec); + switch (pd->model) { + case UDA134X_UDA1340: + case UDA134X_UDA1344: + ret = snd_soc_add_controls(codec, uda1340_snd_controls, + ARRAY_SIZE(uda1340_snd_controls)); + break; + case UDA134X_UDA1341: + ret = snd_soc_add_controls(codec, uda1341_snd_controls, + ARRAY_SIZE(uda1341_snd_controls)); + break; + default: + printk(KERN_ERR "%s unkown codec type: %d", + __func__, pd->model); + return -EINVAL; + } + if (ret < 0) { printk(KERN_ERR "UDA134X: failed to register controls\n"); goto pcm_err; diff --git a/sound/soc/codecs/uda1380.c b/sound/soc/codecs/uda1380.c index e6bf084..a957b43 100644 --- a/sound/soc/codecs/uda1380.c +++ b/sound/soc/codecs/uda1380.c @@ -271,21 +271,6 @@ static const struct snd_kcontrol_new uda1380_snd_controls[] = { SOC_SINGLE("AGC Switch", UDA1380_AGC, 0, 1, 0), }; -/* add non dapm controls */ -static int uda1380_add_controls(struct snd_soc_codec *codec) -{ - int err, i; - - for (i = 0; i < ARRAY_SIZE(uda1380_snd_controls); i++) { - err = snd_ctl_add(codec->card, - snd_soc_cnew(&uda1380_snd_controls[i], codec, NULL)); - if (err < 0) - return err; - } - - return 0; -} - /* Input mux */ static const struct snd_kcontrol_new uda1380_input_mux_control = SOC_DAPM_ENUM("Route", uda1380_input_sel_enum); @@ -675,7 +660,8 @@ static int uda1380_init(struct snd_soc_device *socdev, int dac_clk) } /* uda1380 init */ - uda1380_add_controls(codec); + snd_soc_add_controls(codec, uda1380_snd_controls, + ARRAY_SIZE(uda1380_snd_controls)); uda1380_add_widgets(codec); ret = snd_soc_init_card(socdev); if (ret < 0) { diff --git a/sound/soc/codecs/wm8350.c b/sound/soc/codecs/wm8350.c index 35d9975..c7296ae 100644 --- a/sound/soc/codecs/wm8350.c +++ b/sound/soc/codecs/wm8350.c @@ -51,10 +51,17 @@ struct wm8350_output { u16 mute; }; +struct wm8350_jack_data { + struct snd_soc_jack *jack; + int report; +}; + struct wm8350_data { struct snd_soc_codec codec; struct wm8350_output out1; struct wm8350_output out2; + struct wm8350_jack_data hpl; + struct wm8350_jack_data hpr; struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)]; }; @@ -775,21 +782,6 @@ static const struct snd_soc_dapm_route audio_map[] = { {"Beep", NULL, "IN3R PGA"}, }; -static int wm8350_add_controls(struct snd_soc_codec *codec) -{ - int err, i; - - for (i = 0; i < ARRAY_SIZE(wm8350_snd_controls); i++) { - err = snd_ctl_add(codec->card, - snd_soc_cnew(&wm8350_snd_controls[i], - codec, NULL)); - if (err < 0) - return err; - } - - return 0; -} - static int wm8350_add_widgets(struct snd_soc_codec *codec) { int ret; @@ -1328,6 +1320,95 @@ static int wm8350_resume(struct platform_device *pdev) return 0; } +static void wm8350_hp_jack_handler(struct wm8350 *wm8350, int irq, void *data) +{ + struct wm8350_data *priv = data; + u16 reg; + int report; + int mask; + struct wm8350_jack_data *jack = NULL; + + switch (irq) { + case WM8350_IRQ_CODEC_JCK_DET_L: + jack = &priv->hpl; + mask = WM8350_JACK_L_LVL; + break; + + case WM8350_IRQ_CODEC_JCK_DET_R: + jack = &priv->hpr; + mask = WM8350_JACK_R_LVL; + break; + + default: + BUG(); + } + + if (!jack->jack) { + dev_warn(wm8350->dev, "Jack interrupt called with no jack\n"); + return; + } + + /* Debounce */ + msleep(200); + + reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS); + if (reg & mask) + report = jack->report; + else + report = 0; + + snd_soc_jack_report(jack->jack, report, jack->report); +} + +/** + * wm8350_hp_jack_detect - Enable headphone jack detection. + * + * @codec: WM8350 codec + * @which: left or right jack detect signal + * @jack: jack to report detection events on + * @report: value to report + * + * Enables the headphone jack detection of the WM8350. + */ +int wm8350_hp_jack_detect(struct snd_soc_codec *codec, enum wm8350_jack which, + struct snd_soc_jack *jack, int report) +{ + struct wm8350_data *priv = codec->private_data; + struct wm8350 *wm8350 = codec->control_data; + int irq; + int ena; + + switch (which) { + case WM8350_JDL: + priv->hpl.jack = jack; + priv->hpl.report = report; + irq = WM8350_IRQ_CODEC_JCK_DET_L; + ena = WM8350_JDL_ENA; + break; + + case WM8350_JDR: + priv->hpr.jack = jack; + priv->hpr.report = report; + irq = WM8350_IRQ_CODEC_JCK_DET_R; + ena = WM8350_JDR_ENA; + break; + + default: + return -EINVAL; + } + + wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA); + wm8350_set_bits(wm8350, WM8350_JACK_DETECT, ena); + + /* Sync status */ + wm8350_hp_jack_handler(wm8350, irq, priv); + + wm8350_unmask_irq(wm8350, irq); + + return 0; +} +EXPORT_SYMBOL_GPL(wm8350_hp_jack_detect); + static struct snd_soc_codec *wm8350_codec; static int wm8350_probe(struct platform_device *pdev) @@ -1381,13 +1462,21 @@ static int wm8350_probe(struct platform_device *pdev) wm8350_set_bits(wm8350, WM8350_ROUT2_VOLUME, WM8350_OUT2_VU | WM8350_OUT2R_MUTE); + wm8350_mask_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L); + wm8350_mask_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R); + wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L, + wm8350_hp_jack_handler, priv); + wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R, + wm8350_hp_jack_handler, priv); + ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); if (ret < 0) { dev_err(&pdev->dev, "failed to create pcms\n"); return ret; } - wm8350_add_controls(codec); + snd_soc_add_controls(codec, wm8350_snd_controls, + ARRAY_SIZE(wm8350_snd_controls)); wm8350_add_widgets(codec); wm8350_set_bias_level(codec, SND_SOC_BIAS_STANDBY); @@ -1411,8 +1500,21 @@ static int wm8350_remove(struct platform_device *pdev) struct snd_soc_device *socdev = platform_get_drvdata(pdev); struct snd_soc_codec *codec = socdev->codec; struct wm8350 *wm8350 = codec->control_data; + struct wm8350_data *priv = codec->private_data; int ret; + wm8350_clear_bits(wm8350, WM8350_JACK_DETECT, + WM8350_JDL_ENA | WM8350_JDR_ENA); + wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA); + + wm8350_mask_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L); + wm8350_mask_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R); + wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L); + wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R); + + priv->hpl.jack = NULL; + priv->hpr.jack = NULL; + /* cancel any work waiting to be queued. */ ret = cancel_delayed_work(&codec->delayed_work); diff --git a/sound/soc/codecs/wm8350.h b/sound/soc/codecs/wm8350.h index cc2887a..d11bd92 100644 --- a/sound/soc/codecs/wm8350.h +++ b/sound/soc/codecs/wm8350.h @@ -17,4 +17,12 @@ extern struct snd_soc_dai wm8350_dai; extern struct snd_soc_codec_device soc_codec_dev_wm8350; +enum wm8350_jack { + WM8350_JDL = 1, + WM8350_JDR = 2, +}; + +int wm8350_hp_jack_detect(struct snd_soc_codec *codec, enum wm8350_jack which, + struct snd_soc_jack *jack, int report); + #endif diff --git a/sound/soc/codecs/wm8510.c b/sound/soc/codecs/wm8510.c index 40f8238..abe7cce 100644 --- a/sound/soc/codecs/wm8510.c +++ b/sound/soc/codecs/wm8510.c @@ -171,22 +171,6 @@ SOC_SINGLE("Capture Boost(+20dB)", WM8510_ADCBOOST, 8, 1, 0), SOC_SINGLE("Mono Playback Switch", WM8510_MONOMIX, 6, 1, 1), }; -/* add non dapm controls */ -static int wm8510_add_controls(struct snd_soc_codec *codec) -{ - int err, i; - - for (i = 0; i < ARRAY_SIZE(wm8510_snd_controls); i++) { - err = snd_ctl_add(codec->card, - snd_soc_cnew(&wm8510_snd_controls[i], codec, - NULL)); - if (err < 0) - return err; - } - - return 0; -} - /* Speaker Output Mixer */ static const struct snd_kcontrol_new wm8510_speaker_mixer_controls[] = { SOC_DAPM_SINGLE("Line Bypass Switch", WM8510_SPKMIX, 1, 1, 0), @@ -656,7 +640,8 @@ static int wm8510_init(struct snd_soc_device *socdev) /* power on device */ codec->bias_level = SND_SOC_BIAS_OFF; wm8510_set_bias_level(codec, SND_SOC_BIAS_STANDBY); - wm8510_add_controls(codec); + snd_soc_add_controls(codec, wm8510_snd_controls, + ARRAY_SIZE(wm8510_snd_controls)); wm8510_add_widgets(codec); ret = snd_soc_init_card(socdev); if (ret < 0) { diff --git a/sound/soc/codecs/wm8580.c b/sound/soc/codecs/wm8580.c index d004e58..9b75a37 100644 --- a/sound/soc/codecs/wm8580.c +++ b/sound/soc/codecs/wm8580.c @@ -330,20 +330,6 @@ SOC_DOUBLE("ADC Mute Switch", WM8580_ADC_CONTROL1, 0, 1, 1, 0), SOC_SINGLE("ADC High-Pass Filter Switch", WM8580_ADC_CONTROL1, 4, 1, 0), }; -/* Add non-DAPM controls */ -static int wm8580_add_controls(struct snd_soc_codec *codec) -{ - int err, i; - - for (i = 0; i < ARRAY_SIZE(wm8580_snd_controls); i++) { - err = snd_ctl_add(codec->card, - snd_soc_cnew(&wm8580_snd_controls[i], - codec, NULL)); - if (err < 0) - return err; - } - return 0; -} static const struct snd_soc_dapm_widget wm8580_dapm_widgets[] = { SND_SOC_DAPM_DAC("DAC1", "Playback", WM8580_PWRDN1, 2, 1), SND_SOC_DAPM_DAC("DAC2", "Playback", WM8580_PWRDN1, 3, 1), @@ -866,7 +852,8 @@ static int wm8580_init(struct snd_soc_device *socdev) goto pcm_err; } - wm8580_add_controls(codec); + snd_soc_add_controls(codec, wm8580_snd_controls, + ARRAY_SIZE(wm8580_snd_controls)); wm8580_add_widgets(codec); ret = snd_soc_init_card(socdev); diff --git a/sound/soc/codecs/wm8711.c b/sound/soc/codecs/wm8711.c new file mode 100644 index 0000000..9cf16a4 --- /dev/null +++ b/sound/soc/codecs/wm8711.c @@ -0,0 +1,689 @@ +/* + * wm8711.c -- WM8711 ALSA SoC Audio driver + * + * Copyright 2006 Wolfson Microelectronics + * + * Author: Mike Arthur + * + * Based on wm8731.c by Richard Purdie + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "wm8711.h" + +#define AUDIO_NAME "wm8711" +#define WM8711_VERSION "0.3" + +/* codec private data */ +struct wm8711_priv { + unsigned int sysclk; +}; + +/* + * wm8711 register cache + * We can't read the WM8711 register space when we are + * using 2 wire for device control, so we cache them instead. + * There is no point in caching the reset register + */ +static const u16 wm8711_reg[WM8711_CACHEREGNUM] = { + 0x0079, 0x0079, 0x000a, 0x0008, + 0x009f, 0x000a, 0x0000, 0x0000 +}; + +/* + * read wm8711 register cache + */ +static inline unsigned int wm8711_read_reg_cache(struct snd_soc_codec *codec, + unsigned int reg) +{ + u16 *cache = codec->reg_cache; + if (reg == WM8711_RESET) + return 0; + if (reg >= WM8711_CACHEREGNUM) + return -1; + return cache[reg]; +} + +/* + * write wm8711 register cache + */ +static inline void wm8711_write_reg_cache(struct snd_soc_codec *codec, + u16 reg, unsigned int value) +{ + u16 *cache = codec->reg_cache; + if (reg >= WM8711_CACHEREGNUM) + return; + cache[reg] = value; +} + +/* + * write to the WM8711 register space + */ +static int wm8711_write(struct snd_soc_codec *codec, unsigned int reg, + unsigned int value) +{ + u8 data[2]; + + /* data is + * D15..D9 WM8753 register offset + * D8...D0 register data + */ + data[0] = (reg << 1) | ((value >> 8) & 0x0001); + data[1] = value & 0x00ff; + + wm8711_write_reg_cache(codec, reg, value); + if (codec->hw_write(codec->control_data, data, 2) == 2) + return 0; + else + return -EIO; +} + +#define wm8711_reset(c) wm8711_write(c, WM8711_RESET, 0) + +static const struct snd_kcontrol_new wm8711_snd_controls[] = { + +SOC_DOUBLE_R("Master Playback Volume", WM8711_LOUT1V, WM8711_ROUT1V, + 0, 127, 0), +SOC_DOUBLE_R("Master Playback ZC Switch", WM8711_LOUT1V, WM8711_ROUT1V, + 7, 1, 0), + +}; + +/* add non dapm controls */ +static int wm8711_add_controls(struct snd_soc_codec *codec) +{ + int err, i; + + for (i = 0; i < ARRAY_SIZE(wm8711_snd_controls); i++) { + err = snd_ctl_add(codec->card, + snd_soc_cnew(&wm8711_snd_controls[i], codec, + NULL)); + if (err < 0) + return err; + } + + return 0; +} + +/* Output Mixer */ +static const struct snd_kcontrol_new wm8711_output_mixer_controls[] = { +SOC_DAPM_SINGLE("Line Bypass Switch", WM8711_APANA, 3, 1, 0), +SOC_DAPM_SINGLE("HiFi Playback Switch", WM8711_APANA, 4, 1, 0), +}; + +static const struct snd_soc_dapm_widget wm8711_dapm_widgets[] = { +SND_SOC_DAPM_MIXER("Output Mixer", WM8711_PWR, 4, 1, + &wm8711_output_mixer_controls[0], + ARRAY_SIZE(wm8711_output_mixer_controls)), +SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM8711_PWR, 3, 1), +SND_SOC_DAPM_OUTPUT("LOUT"), +SND_SOC_DAPM_OUTPUT("LHPOUT"), +SND_SOC_DAPM_OUTPUT("ROUT"), +SND_SOC_DAPM_OUTPUT("RHPOUT"), +}; + +static const struct snd_soc_dapm_route intercon[] = { + /* output mixer */ + {"Output Mixer", "Line Bypass Switch", "Line Input"}, + {"Output Mixer", "HiFi Playback Switch", "DAC"}, + + /* outputs */ + {"RHPOUT", NULL, "Output Mixer"}, + {"ROUT", NULL, "Output Mixer"}, + {"LHPOUT", NULL, "Output Mixer"}, + {"LOUT", NULL, "Output Mixer"}, +}; + +static int wm8711_add_widgets(struct snd_soc_codec *codec) +{ + snd_soc_dapm_new_controls(codec, wm8711_dapm_widgets, + ARRAY_SIZE(wm8711_dapm_widgets)); + + snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); + + snd_soc_dapm_new_widgets(codec); + return 0; +} + +struct _coeff_div { + u32 mclk; + u32 rate; + u16 fs; + u8 sr:4; + u8 bosr:1; + u8 usb:1; +}; + +/* codec mclk clock divider coefficients */ +static const struct _coeff_div coeff_div[] = { + /* 48k */ + {12288000, 48000, 256, 0x0, 0x0, 0x0}, + {18432000, 48000, 384, 0x0, 0x1, 0x0}, + {12000000, 48000, 250, 0x0, 0x0, 0x1}, + + /* 32k */ + {12288000, 32000, 384, 0x6, 0x0, 0x0}, + {18432000, 32000, 576, 0x6, 0x1, 0x0}, + {12000000, 32000, 375, 0x6, 0x0, 0x1}, + + /* 8k */ + {12288000, 8000, 1536, 0x3, 0x0, 0x0}, + {18432000, 8000, 2304, 0x3, 0x1, 0x0}, + {11289600, 8000, 1408, 0xb, 0x0, 0x0}, + {16934400, 8000, 2112, 0xb, 0x1, 0x0}, + {12000000, 8000, 1500, 0x3, 0x0, 0x1}, + + /* 96k */ + {12288000, 96000, 128, 0x7, 0x0, 0x0}, + {18432000, 96000, 192, 0x7, 0x1, 0x0}, + {12000000, 96000, 125, 0x7, 0x0, 0x1}, + + /* 44.1k */ + {11289600, 44100, 256, 0x8, 0x0, 0x0}, + {16934400, 44100, 384, 0x8, 0x1, 0x0}, + {12000000, 44100, 272, 0x8, 0x1, 0x1}, + + /* 88.2k */ + {11289600, 88200, 128, 0xf, 0x0, 0x0}, + {16934400, 88200, 192, 0xf, 0x1, 0x0}, + {12000000, 88200, 136, 0xf, 0x1, 0x1}, +}; + +static inline int get_coeff(int mclk, int rate) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(coeff_div); i++) { + if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk) + return i; + } + return 0; +} + +static int wm8711_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->codec; + struct wm8711_priv *wm8711 = codec->private_data; + u16 iface = wm8711_read_reg_cache(codec, WM8711_IFACE) & 0xfffc; + int i = get_coeff(wm8711->sysclk, params_rate(params)); + u16 srate = (coeff_div[i].sr << 2) | + (coeff_div[i].bosr << 1) | coeff_div[i].usb; + + wm8711_write(codec, WM8711_SRATE, srate); + + /* bit size */ + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + break; + case SNDRV_PCM_FORMAT_S20_3LE: + iface |= 0x0004; + break; + case SNDRV_PCM_FORMAT_S24_LE: + iface |= 0x0008; + break; + } + + wm8711_write(codec, WM8711_IFACE, iface); + return 0; +} + +static int wm8711_pcm_prepare(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->codec; + + /* set active */ + wm8711_write(codec, WM8711_ACTIVE, 0x0001); + + return 0; +} + +static void wm8711_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->codec; + + /* deactivate */ + if (!codec->active) { + udelay(50); + wm8711_write(codec, WM8711_ACTIVE, 0x0); + } +} + +static int wm8711_mute(struct snd_soc_dai *dai, int mute) +{ + struct snd_soc_codec *codec = dai->codec; + u16 mute_reg = wm8711_read_reg_cache(codec, WM8711_APDIGI) & 0xfff7; + + if (mute) + wm8711_write(codec, WM8711_APDIGI, mute_reg | 0x8); + else + wm8711_write(codec, WM8711_APDIGI, mute_reg); + + return 0; +} + +static int wm8711_set_dai_sysclk(struct snd_soc_dai *codec_dai, + int clk_id, unsigned int freq, int dir) +{ + struct snd_soc_codec *codec = codec_dai->codec; + struct wm8711_priv *wm8711 = codec->private_data; + + switch (freq) { + case 11289600: + case 12000000: + case 12288000: + case 16934400: + case 18432000: + wm8711->sysclk = freq; + return 0; + } + return -EINVAL; +} + +static int wm8711_set_dai_fmt(struct snd_soc_dai *codec_dai, + unsigned int fmt) +{ + struct snd_soc_codec *codec = codec_dai->codec; + u16 iface = 0; + + /* set master/slave audio interface */ + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + iface |= 0x0040; + break; + case SND_SOC_DAIFMT_CBS_CFS: + break; + default: + return -EINVAL; + } + + /* interface format */ + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + iface |= 0x0002; + break; + case SND_SOC_DAIFMT_RIGHT_J: + break; + case SND_SOC_DAIFMT_LEFT_J: + iface |= 0x0001; + break; + case SND_SOC_DAIFMT_DSP_A: + iface |= 0x0003; + break; + case SND_SOC_DAIFMT_DSP_B: + iface |= 0x0013; + break; + default: + return -EINVAL; + } + + /* clock inversion */ + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + case SND_SOC_DAIFMT_IB_IF: + iface |= 0x0090; + break; + case SND_SOC_DAIFMT_IB_NF: + iface |= 0x0080; + break; + case SND_SOC_DAIFMT_NB_IF: + iface |= 0x0010; + break; + default: + return -EINVAL; + } + + /* set iface */ + wm8711_write(codec, WM8711_IFACE, iface); + return 0; +} + + +static int wm8711_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level) +{ + u16 reg = wm8711_read_reg_cache(codec, WM8711_PWR) & 0xff7f; + + switch (level) { + case SND_SOC_BIAS_ON: + wm8711_write(codec, WM8711_PWR, reg); + break; + case SND_SOC_BIAS_PREPARE: + break; + case SND_SOC_BIAS_STANDBY: + wm8711_write(codec, WM8711_PWR, reg | 0x0040); + break; + case SND_SOC_BIAS_OFF: + wm8711_write(codec, WM8711_ACTIVE, 0x0); + wm8711_write(codec, WM8711_PWR, 0xffff); + break; + } + codec->bias_level = level; + return 0; +} + +#define WM8711_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ + SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\ + SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\ + SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |\ + SNDRV_PCM_RATE_96000) + +#define WM8711_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ + SNDRV_PCM_FMTBIT_S24_LE) + +struct snd_soc_dai wm8711_dai = { + .name = "WM8711", + .playback = { + .stream_name = "Playback", + .channels_min = 1, + .channels_max = 2, + .rates = WM8711_RATES, + .formats = WM8711_FORMATS,}, + .ops = { + .prepare = wm8711_pcm_prepare, + .hw_params = wm8711_hw_params, + .shutdown = wm8711_shutdown, + .digital_mute = wm8711_mute, + .set_sysclk = wm8711_set_dai_sysclk, + .set_fmt = wm8711_set_dai_fmt, + }, +}; +EXPORT_SYMBOL_GPL(wm8711_dai); + +static int wm8711_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + + wm8711_write(codec, WM8711_ACTIVE, 0x0); + wm8711_set_bias_level(codec, SND_SOC_BIAS_OFF); + return 0; +} + +static int wm8711_resume(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + int i; + u8 data[2]; + u16 *cache = codec->reg_cache; + + /* Sync reg_cache with the hardware */ + for (i = 0; i < ARRAY_SIZE(wm8711_reg); i++) { + data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001); + data[1] = cache[i] & 0x00ff; + codec->hw_write(codec->control_data, data, 2); + } + wm8711_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + wm8711_set_bias_level(codec, codec->suspend_bias_level); + return 0; +} + +/* + * initialise the WM8711 driver + * register the mixer and dsp interfaces with the kernel + */ +static int wm8711_init(struct snd_soc_device *socdev) +{ + struct snd_soc_codec *codec = socdev->codec; + int reg, ret = 0; + + codec->name = "WM8711"; + codec->owner = THIS_MODULE; + codec->read = wm8711_read_reg_cache; + codec->write = wm8711_write; + codec->set_bias_level = wm8711_set_bias_level; + codec->dai = &wm8711_dai; + codec->num_dai = 1; + codec->reg_cache_size = ARRAY_SIZE(wm8711_reg); + codec->reg_cache = kmemdup(wm8711_reg, sizeof(wm8711_reg), GFP_KERNEL); + + if (codec->reg_cache == NULL) + return -ENOMEM; + + wm8711_reset(codec); + + /* register pcms */ + ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); + if (ret < 0) { + printk(KERN_ERR "wm8711: failed to create pcms\n"); + goto pcm_err; + } + + /* power on device */ + wm8711_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + + /* set the update bits */ + reg = wm8711_read_reg_cache(codec, WM8711_LOUT1V); + wm8711_write(codec, WM8711_LOUT1V, reg | 0x0100); + reg = wm8711_read_reg_cache(codec, WM8711_ROUT1V); + wm8711_write(codec, WM8711_ROUT1V, reg | 0x0100); + + wm8711_add_controls(codec); + wm8711_add_widgets(codec); + ret = snd_soc_init_card(socdev); + if (ret < 0) { + printk(KERN_ERR "wm8711: failed to register card\n"); + goto card_err; + } + return ret; + +card_err: + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); +pcm_err: + kfree(codec->reg_cache); + return ret; +} + +static struct snd_soc_device *wm8711_socdev; + +#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) + +/* + * WM8711 2 wire address is determined by GPIO5 + * state during powerup. + * low = 0x1a + * high = 0x1b + */ +#define I2C_DRIVERID_WM8711 0xfefe /* liam - need a proper id */ + +static unsigned short normal_i2c[] = { 0, I2C_CLIENT_END }; + +/* Magic definition of all other variables and things */ +I2C_CLIENT_INSMOD; + +static struct i2c_driver wm8711_i2c_driver; +static struct i2c_client client_template; + +/* If the i2c layer weren't so broken, we could pass this kind of data + around */ + +static int wm8711_codec_probe(struct i2c_adapter *adap, int addr, int kind) +{ + struct snd_soc_device *socdev = wm8711_socdev; + struct wm8711_setup_data *setup = socdev->codec_data; + struct snd_soc_codec *codec = socdev->codec; + struct i2c_client *i2c; + int ret; + + if (addr != setup->i2c_address) + return -ENODEV; + + client_template.adapter = adap; + client_template.addr = addr; + + i2c = kmemdup(&client_template, sizeof(client_template), GFP_KERNEL); + if (i2c == NULL) { + kfree(codec); + return -ENOMEM; + } + + i2c_set_clientdata(i2c, codec); + + codec->control_data = i2c; + + ret = i2c_attach_client(i2c); + if (ret < 0) { + pr_err("failed to attach codec at addr %x\n", addr); + goto err; + } + + ret = wm8711_init(socdev); + if (ret < 0) { + pr_err("failed to initialise WM8711\n"); + goto err; + } + return ret; + +err: + kfree(codec); + kfree(i2c); + return ret; +} + +static int wm8711_i2c_detach(struct i2c_client *client) +{ + struct snd_soc_codec *codec = i2c_get_clientdata(client); + + i2c_detach_client(client); + kfree(codec->reg_cache); + kfree(client); + return 0; +} + +static int wm8711_i2c_attach(struct i2c_adapter *adap) +{ + return i2c_probe(adap, &addr_data, wm8711_codec_probe); +} + +/* corgi i2c codec control layer */ +static struct i2c_driver wm8711_i2c_driver = { + .driver = { + .name = "WM8711 I2C Codec", + .owner = THIS_MODULE, + }, + .id = I2C_DRIVERID_WM8711, + .attach_adapter = wm8711_i2c_attach, + .detach_client = wm8711_i2c_detach, + .command = NULL, +}; + +static struct i2c_client client_template = { + .name = "WM8711", + .driver = &wm8711_i2c_driver, +}; +#endif + +static int wm8711_probe(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct wm8711_setup_data *setup; + struct snd_soc_codec *codec; + struct wm8711_priv *wm8711; + int ret = 0; + + pr_info("WM8711 Audio Codec %s", WM8711_VERSION); + + setup = socdev->codec_data; + codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); + if (codec == NULL) + return -ENOMEM; + + wm8711 = kzalloc(sizeof(struct wm8711_priv), GFP_KERNEL); + if (wm8711 == NULL) { + kfree(codec); + return -ENOMEM; + } + + codec->private_data = wm8711; + socdev->codec = codec; + mutex_init(&codec->mutex); + INIT_LIST_HEAD(&codec->dapm_widgets); + INIT_LIST_HEAD(&codec->dapm_paths); + + wm8711_socdev = socdev; +#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) + if (setup->i2c_address) { + normal_i2c[0] = setup->i2c_address; + codec->hw_write = (hw_write_t)i2c_master_send; + ret = i2c_add_driver(&wm8711_i2c_driver); + if (ret != 0) + printk(KERN_ERR "can't add i2c driver"); + } +#else + /* Add other interfaces here */ +#endif + return ret; +} + +/* power down chip */ +static int wm8711_remove(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + + if (codec->control_data) + wm8711_set_bias_level(codec, SND_SOC_BIAS_OFF); + + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); +#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) + i2c_del_driver(&wm8711_i2c_driver); +#endif + kfree(codec->private_data); + kfree(codec); + + return 0; +} + +struct snd_soc_codec_device soc_codec_dev_wm8711 = { + .probe = wm8711_probe, + .remove = wm8711_remove, + .suspend = wm8711_suspend, + .resume = wm8711_resume, +}; +EXPORT_SYMBOL_GPL(soc_codec_dev_wm8711); + +static int __init wm8711_modinit(void) +{ + return snd_soc_register_dai(&wm8711_dai); +} +module_init(wm8711_modinit); + +static void __exit wm8711_exit(void) +{ + snd_soc_unregister_dai(&wm8711_dai); +} +module_exit(wm8711_exit); + +MODULE_DESCRIPTION("ASoC WM8711 driver"); +MODULE_AUTHOR("Mike Arthur"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/wm8711.h b/sound/soc/codecs/wm8711.h new file mode 100644 index 0000000..381e84a --- /dev/null +++ b/sound/soc/codecs/wm8711.h @@ -0,0 +1,42 @@ +/* + * wm8711.h -- WM8711 Soc Audio driver + * + * Copyright 2006 Wolfson Microelectronics + * + * Author: Mike Arthur + * + * Based on wm8731.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _WM8711_H +#define _WM8711_H + +/* WM8711 register space */ + +#define WM8711_LOUT1V 0x02 +#define WM8711_ROUT1V 0x03 +#define WM8711_APANA 0x04 +#define WM8711_APDIGI 0x05 +#define WM8711_PWR 0x06 +#define WM8711_IFACE 0x07 +#define WM8711_SRATE 0x08 +#define WM8711_ACTIVE 0x09 +#define WM8711_RESET 0x0f + +#define WM8711_CACHEREGNUM 8 + +#define WM8711_SYSCLK 0 +#define WM8711_DAI 0 + +struct wm8711_setup_data { + unsigned short i2c_address; +}; + +extern struct snd_soc_dai wm8711_dai; +extern struct snd_soc_codec_device soc_codec_dev_wm8711; + +#endif diff --git a/sound/soc/codecs/wm8728.c b/sound/soc/codecs/wm8728.c index 80b1198..defa310 100644 --- a/sound/soc/codecs/wm8728.c +++ b/sound/soc/codecs/wm8728.c @@ -92,21 +92,6 @@ SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8728_DACLVOL, WM8728_DACRVOL, SOC_SINGLE("Deemphasis", WM8728_DACCTL, 1, 1, 0), }; -static int wm8728_add_controls(struct snd_soc_codec *codec) -{ - int err, i; - - for (i = 0; i < ARRAY_SIZE(wm8728_snd_controls); i++) { - err = snd_ctl_add(codec->card, - snd_soc_cnew(&wm8728_snd_controls[i], - codec, NULL)); - if (err < 0) - return err; - } - - return 0; -} - /* * DAPM controls. */ @@ -330,7 +315,8 @@ static int wm8728_init(struct snd_soc_device *socdev) /* power on device */ wm8728_set_bias_level(codec, SND_SOC_BIAS_STANDBY); - wm8728_add_controls(codec); + snd_soc_add_controls(codec, wm8728_snd_controls, + ARRAY_SIZE(wm8728_snd_controls)); wm8728_add_widgets(codec); ret = snd_soc_init_card(socdev); if (ret < 0) { diff --git a/sound/soc/codecs/wm8731.c b/sound/soc/codecs/wm8731.c index c444b9f..96d6e1a 100644 --- a/sound/soc/codecs/wm8731.c +++ b/sound/soc/codecs/wm8731.c @@ -129,22 +129,6 @@ SOC_SINGLE("Store DC Offset Switch", WM8731_APDIGI, 4, 1, 0), SOC_ENUM("Playback De-emphasis", wm8731_enum[1]), }; -/* add non dapm controls */ -static int wm8731_add_controls(struct snd_soc_codec *codec) -{ - int err, i; - - for (i = 0; i < ARRAY_SIZE(wm8731_snd_controls); i++) { - err = snd_ctl_add(codec->card, - snd_soc_cnew(&wm8731_snd_controls[i], - codec, NULL)); - if (err < 0) - return err; - } - - return 0; -} - /* Output Mixer */ static const struct snd_kcontrol_new wm8731_output_mixer_controls[] = { SOC_DAPM_SINGLE("Line Bypass Switch", WM8731_APANA, 3, 1, 0), @@ -543,7 +527,8 @@ static int wm8731_init(struct snd_soc_device *socdev) reg = wm8731_read_reg_cache(codec, WM8731_RINVOL); wm8731_write(codec, WM8731_RINVOL, reg & ~0x0100); - wm8731_add_controls(codec); + snd_soc_add_controls(codec, wm8731_snd_controls, + ARRAY_SIZE(wm8731_snd_controls)); wm8731_add_widgets(codec); ret = snd_soc_init_card(socdev); if (ret < 0) { diff --git a/sound/soc/codecs/wm8750.c b/sound/soc/codecs/wm8750.c index 5997fa6..1578569 100644 --- a/sound/soc/codecs/wm8750.c +++ b/sound/soc/codecs/wm8750.c @@ -231,21 +231,6 @@ SOC_SINGLE("Mono Playback Volume", WM8750_MOUTV, 0, 127, 0), }; -/* add non dapm controls */ -static int wm8750_add_controls(struct snd_soc_codec *codec) -{ - int err, i; - - for (i = 0; i < ARRAY_SIZE(wm8750_snd_controls); i++) { - err = snd_ctl_add(codec->card, - snd_soc_cnew(&wm8750_snd_controls[i], - codec, NULL)); - if (err < 0) - return err; - } - return 0; -} - /* * DAPM Controls */ @@ -816,7 +801,8 @@ static int wm8750_init(struct snd_soc_device *socdev) reg = wm8750_read_reg_cache(codec, WM8750_RINVOL); wm8750_write(codec, WM8750_RINVOL, reg | 0x0100); - wm8750_add_controls(codec); + snd_soc_add_controls(codec, wm8750_snd_controls, + ARRAY_SIZE(wm8750_snd_controls)); wm8750_add_widgets(codec); ret = snd_soc_init_card(socdev); if (ret < 0) { diff --git a/sound/soc/codecs/wm8753.c b/sound/soc/codecs/wm8753.c index 77620ab..6709a55 100644 --- a/sound/soc/codecs/wm8753.c +++ b/sound/soc/codecs/wm8753.c @@ -339,21 +339,6 @@ SOC_ENUM("ADC Data Select", wm8753_enum[27]), SOC_ENUM("ROUT2 Phase", wm8753_enum[28]), }; -/* add non dapm controls */ -static int wm8753_add_controls(struct snd_soc_codec *codec) -{ - int err, i; - - for (i = 0; i < ARRAY_SIZE(wm8753_snd_controls); i++) { - err = snd_ctl_add(codec->card, - snd_soc_cnew(&wm8753_snd_controls[i], - codec, NULL)); - if (err < 0) - return err; - } - return 0; -} - /* * _DAPM_ Controls */ @@ -1610,7 +1595,8 @@ static int wm8753_init(struct snd_soc_device *socdev) reg = wm8753_read_reg_cache(codec, WM8753_RINVOL); wm8753_write(codec, WM8753_RINVOL, reg | 0x0100); - wm8753_add_controls(codec); + snd_soc_add_controls(codec, wm8753_snd_controls, + ARRAY_SIZE(wm8753_snd_controls)); wm8753_add_widgets(codec); ret = snd_soc_init_card(socdev); if (ret < 0) { diff --git a/sound/soc/codecs/wm8772.c b/sound/soc/codecs/wm8772.c new file mode 100644 index 0000000..ebb6d20 --- /dev/null +++ b/sound/soc/codecs/wm8772.c @@ -0,0 +1,605 @@ +/* + * wm8772.c -- WM8772 ALSA Soc Audio driver + * + * Copyright 2005 Wolfson Microelectronics PLC. + * Author: Liam Girdwood + * liam.girdwood@wolfsonmicro.com or linux@wolfsonmicro.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "wm8772.h" + +#define AUDIO_NAME "WM8772" +#define WM8772_VERSION "0.4" + +/* codec private data */ +struct wm8772_priv { + unsigned int adcclk; + unsigned int dacclk; +}; + +/* + * wm8772 register cache + * We can't read the WM8772 register space when we + * are using 2 wire for device control, so we cache them instead. + */ +static const u16 wm8772_reg[] = { + 0x00ff, 0x00ff, 0x0120, 0x0000, /* 0 */ + 0x00ff, 0x00ff, 0x00ff, 0x00ff, /* 4 */ + 0x00ff, 0x0000, 0x0080, 0x0040, /* 8 */ + 0x0000 +}; + +/* + * read wm8772 register cache + */ +static inline unsigned int wm8772_read_reg_cache(struct snd_soc_codec * codec, + unsigned int reg) +{ + u16 *cache = codec->reg_cache; + if (reg > WM8772_CACHE_REGNUM) + return -1; + return cache[reg]; +} + +/* + * write wm8772 register cache + */ +static inline void wm8772_write_reg_cache(struct snd_soc_codec * codec, + unsigned int reg, unsigned int value) +{ + u16 *cache = codec->reg_cache; + if (reg > WM8772_CACHE_REGNUM) + return; + cache[reg] = value; +} + +static int wm8772_write(struct snd_soc_codec * codec, unsigned int reg, + unsigned int value) +{ + u8 data[2]; + + /* data is + * D15..D9 WM8772 register offset + * D8...D0 register data + */ + data[0] = (reg << 1) | ((value >> 8) & 0x0001); + data[1] = value & 0x00ff; + + wm8772_write_reg_cache (codec, reg, value); + if (codec->hw_write(codec->control_data, data, 2) == 2) + return 0; + else + return -1; +} + +#define wm8772_reset(c) wm8772_write(c, WM8772_RESET, 0) + +/* + * WM8772 Controls + */ +static const char *wm8772_zero_flag[] = {"All Ch", "Ch 1", "Ch 2", "Ch3"}; + +static const struct soc_enum wm8772_enum[] = { +SOC_ENUM_SINGLE(WM8772_DACCTRL, 0, 4, wm8772_zero_flag), +}; + +static const struct snd_kcontrol_new wm8772_snd_controls[] = { + +SOC_SINGLE("Left1 Playback Volume", WM8772_LDAC1VOL, 0, 255, 0), +SOC_SINGLE("Left2 Playback Volume", WM8772_LDAC2VOL, 0, 255, 0), +SOC_SINGLE("Left3 Playback Volume", WM8772_LDAC3VOL, 0, 255, 0), +SOC_SINGLE("Right1 Playback Volume", WM8772_RDAC1VOL, 0, 255, 0), +SOC_SINGLE("Right1 Playback Volume", WM8772_RDAC2VOL, 0, 255, 0), +SOC_SINGLE("Right1 Playback Volume", WM8772_RDAC3VOL, 0, 255, 0), +SOC_SINGLE("Master Playback Volume", WM8772_MDACVOL, 0, 255, 0), + +SOC_SINGLE("Playback Switch", WM8772_DACCH, 0, 1, 0), +SOC_SINGLE("Capture Switch", WM8772_ADCCTRL, 2, 1, 0), + +SOC_SINGLE("Demp1 Playback Switch", WM8772_DACCTRL, 6, 1, 0), +SOC_SINGLE("Demp2 Playback Switch", WM8772_DACCTRL, 7, 1, 0), +SOC_SINGLE("Demp3 Playback Switch", WM8772_DACCTRL, 8, 1, 0), + +SOC_SINGLE("Phase Invert 1 Switch", WM8772_IFACE, 6, 1, 0), +SOC_SINGLE("Phase Invert 2 Switch", WM8772_IFACE, 7, 1, 0), +SOC_SINGLE("Phase Invert 3 Switch", WM8772_IFACE, 8, 1, 0), + +SOC_SINGLE("Playback ZC Switch", WM8772_DACCTRL, 0, 1, 0), + +SOC_SINGLE("Capture High Pass Switch", WM8772_ADCCTRL, 3, 1, 0), +}; + +/* add non dapm controls */ +static int wm8772_add_controls(struct snd_soc_codec *codec) +{ + int err, i; + + for (i = 0; i < ARRAY_SIZE(wm8772_snd_controls); i++) { + err = snd_ctl_add(codec->card, + snd_soc_cnew(&wm8772_snd_controls[i],codec, NULL)); + if (err < 0) + return err; + } + return 0; +} + +static int wm8772_set_dai_sysclk(struct snd_soc_dai *codec_dai, + int clk_id, unsigned int freq, int dir) +{ + struct snd_soc_codec *codec = codec_dai->codec; + struct wm8772_priv *wm8772 = codec->private_data; + + switch (freq) { + case 4096000: + case 5644800: + case 6144000: + case 8192000: + case 8467000: + case 9216000: + case 11289600: + case 12000000: + case 12288000: + case 16934400: + case 18432000: + case 22579200: + case 24576000: + case 33868800: + case 36864000: + if (clk_id == WM8772_DACCLK) { + wm8772->dacclk = freq; + return 0; + } else if (clk_id == WM8772_ADCCLK) { + wm8772->adcclk = freq; + return 0; + } + } + return -EINVAL; +} + +static int wm8772_set_dac_dai_fmt(struct snd_soc_dai *codec_dai, + unsigned int fmt) +{ + struct snd_soc_codec *codec = codec_dai->codec; + u16 diface = wm8772_read_reg_cache(codec, WM8772_IFACE) & 0x1f0; + u16 diface_ctrl = wm8772_read_reg_cache(codec, WM8772_DACRATE) & 0x1ef; + + /* set master/slave audio interface */ + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + diface_ctrl |= 0x0010; + break; + case SND_SOC_DAIFMT_CBS_CFS: + break; + default: + return -EINVAL; + } + + /* interface format */ + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + diface |= 0x0002; + break; + case SND_SOC_DAIFMT_RIGHT_J: + break; + case SND_SOC_DAIFMT_LEFT_J: + diface |= 0x0001; + break; + case SND_SOC_DAIFMT_DSP_A: + diface |= 0x0003; + break; + case SND_SOC_DAIFMT_DSP_B: + diface |= 0x0007; + break; + default: + return -EINVAL; + } + + /* clock inversion */ + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + case SND_SOC_DAIFMT_IB_NF: + diface |= 0x0008; + break; + default: + return -EINVAL; + } + + wm8772_write(codec, WM8772_DACRATE, diface_ctrl); + wm8772_write(codec, WM8772_IFACE, diface); + return 0; +} + +static int wm8772_set_adc_dai_fmt(struct snd_soc_dai *codec_dai, + unsigned int fmt) +{ + struct snd_soc_codec *codec = codec_dai->codec; + u16 aiface = 0; + u16 aiface_ctrl = wm8772_read_reg_cache(codec, WM8772_ADCCTRL) & 0x1cf; + + /* set master/slave audio interface */ + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + aiface |= 0x0010; + break; + case SND_SOC_DAIFMT_CBS_CFS: + break; + default: + return -EINVAL; + } + + /* interface format */ + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + aiface |= 0x0002; + break; + case SND_SOC_DAIFMT_RIGHT_J: + break; + case SND_SOC_DAIFMT_LEFT_J: + aiface |= 0x0001; + break; + case SND_SOC_DAIFMT_DSP_A: + aiface |= 0x0003; + break; + case SND_SOC_DAIFMT_DSP_B: + aiface |= 0x0003; + aiface_ctrl |= 0x0010; + break; + default: + return -EINVAL; + } + + /* clock inversion */ + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + case SND_SOC_DAIFMT_IB_NF: + aiface_ctrl |= 0x0020; + break; + default: + return -EINVAL; + } + + wm8772_write(codec, WM8772_ADCCTRL, aiface_ctrl); + wm8772_write(codec, WM8772_ADCRATE, aiface); + return 0; +} + +static int wm8772_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->codec; + struct wm8772_priv *wm8772 = codec->private_data; + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + + u16 diface = wm8772_read_reg_cache(codec, WM8772_IFACE) & 0x1cf; + u16 diface_ctrl = wm8772_read_reg_cache(codec, WM8772_DACRATE) & 0x3f; + + /* bit size */ + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + break; + case SNDRV_PCM_FORMAT_S20_3LE: + diface |= 0x0010; + break; + case SNDRV_PCM_FORMAT_S24_3LE: + diface |= 0x0020; + break; + case SNDRV_PCM_FORMAT_S32_LE: + diface |= 0x0030; + break; + } + + /* set rate */ + switch (wm8772->dacclk / params_rate(params)) { + case 768: + diface_ctrl |= (0x5 << 6); + break; + case 512: + diface_ctrl |= (0x4 << 6); + break; + case 384: + diface_ctrl |= (0x3 << 6); + break; + case 256: + diface_ctrl |= (0x2 << 6); + break; + case 192: + diface_ctrl |= (0x1 << 6); + break; + } + + wm8772_write(codec, WM8772_DACRATE, diface_ctrl); + wm8772_write(codec, WM8772_IFACE, diface); + + } else { + + u16 aiface = wm8772_read_reg_cache(codec, WM8772_ADCRATE) & 0x113; + + /* bit size */ + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + break; + case SNDRV_PCM_FORMAT_S20_3LE: + aiface |= 0x0004; + break; + case SNDRV_PCM_FORMAT_S24_LE: + aiface |= 0x0008; + break; + case SNDRV_PCM_FORMAT_S32_LE: + aiface |= 0x000c; + break; + } + + /* set rate */ + switch (wm8772->adcclk / params_rate(params)) { + case 768: + aiface |= (0x5 << 5); + break; + case 512: + aiface |= (0x4 << 5); + break; + case 384: + aiface |= (0x3 << 5); + break; + case 256: + aiface |= (0x2 << 5); + break; + } + + wm8772_write(codec, WM8772_ADCRATE, aiface); + } + + return 0; +} + +static int wm8772_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level) +{ + u16 master = wm8772_read_reg_cache(codec, WM8772_DACRATE) & 0xffe0; + + switch (level) { + case SND_SOC_BIAS_ON: + wm8772_write(codec, WM8772_DACRATE, master); + break; + case SND_SOC_BIAS_PREPARE: + break; + case SND_SOC_BIAS_STANDBY: + wm8772_write(codec, WM8772_DACRATE, master | 0x0f); + break; + case SND_SOC_BIAS_OFF: + wm8772_write(codec, WM8772_DACRATE, master | 0x1f); + break; + } + codec->bias_level = level; + return 0; +} + +struct snd_soc_dai wm8772_dai[] = { +{ + .name = "WM8772", + .playback = { + .stream_name = "Playback", + .channels_min = 2, + .channels_max = 6, + }, + .ops = { + .hw_params = wm8772_hw_params, + .set_fmt = wm8772_set_dac_dai_fmt, + .set_sysclk = wm8772_set_dai_sysclk, + }, +}, +{ + .name = "WM8772", + .capture = { + .stream_name = "Capture", + .channels_min = 2, + .channels_max = 2, + }, + .ops = { + .hw_params = wm8772_hw_params, + .set_fmt = wm8772_set_adc_dai_fmt, + .set_sysclk = wm8772_set_dai_sysclk, + }, +}, +}; +EXPORT_SYMBOL_GPL(wm8772_dai); + +static int wm8772_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + + wm8772_set_bias_level(codec, SND_SOC_BIAS_OFF); + return 0; +} + +static int wm8772_resume(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + int i; + u8 data[2]; + u16 *cache = codec->reg_cache; + + /* Sync reg_cache with the hardware */ + for (i = 0; i < ARRAY_SIZE(wm8772_reg); i++) { + data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001); + data[1] = cache[i] & 0x00ff; + codec->hw_write(codec->control_data, data, 2); + } + wm8772_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + wm8772_set_bias_level(codec, codec->suspend_bias_level); + return 0; +} + +/* + * initialise the WM8772 driver + * register the mixer and dsp interfaces with the kernel + */ +static int wm8772_init(struct snd_soc_device *socdev) +{ + struct snd_soc_codec *codec = socdev->codec; + int reg, ret = 0; + + codec->name = "WM8772"; + codec->owner = THIS_MODULE; + codec->read = wm8772_read_reg_cache; + codec->write = wm8772_write; + codec->set_bias_level = wm8772_set_bias_level; + codec->dai = wm8772_dai; + codec->num_dai = 1; + codec->reg_cache_size = ARRAY_SIZE(wm8772_reg); + codec->reg_cache = kmemdup(wm8772_reg, sizeof(wm8772_reg), GFP_KERNEL); + + if (codec->reg_cache == NULL) + return -ENOMEM; + + wm8772_reset(codec); + + /* register pcms */ + ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); + if(ret < 0) { + printk(KERN_ERR "wm8772: failed to create pcms\n"); + goto pcm_err; + } + + /* power on device */ + wm8772_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + + /* set the update bits */ + reg = wm8772_read_reg_cache(codec, WM8772_MDACVOL); + wm8772_write(codec, WM8772_MDACVOL, reg | 0x0100); + reg = wm8772_read_reg_cache(codec, WM8772_LDAC1VOL); + wm8772_write(codec, WM8772_LDAC1VOL, reg | 0x0100); + reg = wm8772_read_reg_cache(codec, WM8772_LDAC2VOL); + wm8772_write(codec, WM8772_LDAC2VOL, reg | 0x0100); + reg = wm8772_read_reg_cache(codec, WM8772_LDAC3VOL); + wm8772_write(codec, WM8772_LDAC3VOL, reg | 0x0100); + reg = wm8772_read_reg_cache(codec, WM8772_RDAC1VOL); + wm8772_write(codec, WM8772_RDAC1VOL, reg | 0x0100); + reg = wm8772_read_reg_cache(codec, WM8772_RDAC2VOL); + wm8772_write(codec, WM8772_RDAC2VOL, reg | 0x0100); + reg = wm8772_read_reg_cache(codec, WM8772_RDAC3VOL); + wm8772_write(codec, WM8772_RDAC3VOL, reg | 0x0100); + + wm8772_add_controls(codec); + ret = snd_soc_init_card(socdev); + if (ret < 0) { + printk(KERN_ERR "wm8772: failed to register card\n"); + goto card_err; + } + return ret; + +card_err: + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); +pcm_err: + kfree(codec->reg_cache); + return ret; +} + +static struct snd_soc_device *wm8772_socdev; + +static int wm8772_probe(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct wm8772_setup_data *setup; + struct snd_soc_codec *codec; + struct wm8772_priv *wm8772; + int ret = 0; + + printk(KERN_INFO "WM8772 Audio Codec %s", WM8772_VERSION); + + setup = socdev->codec_data; + codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); + if (codec == NULL) + return -ENOMEM; + + wm8772 = kzalloc(sizeof(struct wm8772_priv), GFP_KERNEL); + if (wm8772 == NULL) { + kfree(codec); + return -ENOMEM; + } + + codec->private_data = wm8772; + socdev->codec = codec; + mutex_init(&codec->mutex); + INIT_LIST_HEAD(&codec->dapm_widgets); + INIT_LIST_HEAD(&codec->dapm_paths); + + wm8772_socdev = socdev; + + /* Add other interfaces here */ + /* FIXME: Do SPI device probe here */ + + return ret; +} + +/* power down chip */ +static int wm8772_remove(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + + if (codec->control_data) + wm8772_set_bias_level(codec, SND_SOC_BIAS_OFF); + + snd_soc_free_pcms(socdev); + kfree(codec->private_data); + kfree(codec->reg_cache); + kfree(codec); + + return 0; +} + +struct snd_soc_codec_device soc_codec_dev_wm8772 = { + .probe = wm8772_probe, + .remove = wm8772_remove, + .suspend = wm8772_suspend, + .resume = wm8772_resume, +}; + +EXPORT_SYMBOL_GPL(soc_codec_dev_wm8772); + +static int __init wm8772_modinit(void) +{ + return snd_soc_register_dais(wm8772_dai, ARRAY_SIZE(wm8772_dai)); +} +module_init(wm8772_modinit); + +static void __exit wm8772_exit(void) +{ + snd_soc_unregister_dais(wm8772_dai, ARRAY_SIZE(wm8772_dai)); +} +module_exit(wm8772_exit); + +MODULE_DESCRIPTION("ASoC WM8772 driver"); +MODULE_AUTHOR("Liam Girdwood"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/wm8772.h b/sound/soc/codecs/wm8772.h new file mode 100644 index 0000000..3f1b840 --- /dev/null +++ b/sound/soc/codecs/wm8772.h @@ -0,0 +1,46 @@ +/* + * wm8772.h -- audio driver for WM8772 + * + * Copyright 2005 Wolfson Microelectronics PLC. + * Author: Liam Girdwood + * liam.girdwood@wolfsonmicro.com or linux@wolfsonmicro.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef _WM8772_H +#define _WM8772_H + +/* WM8772 register space */ + +#define WM8772_LDAC1VOL 0x00 +#define WM8772_RDAC1VOL 0x01 +#define WM8772_DACCH 0x02 +#define WM8772_IFACE 0x03 +#define WM8772_LDAC2VOL 0x04 +#define WM8772_RDAC2VOL 0x05 +#define WM8772_LDAC3VOL 0x06 +#define WM8772_RDAC3VOL 0x07 +#define WM8772_MDACVOL 0x08 +#define WM8772_DACCTRL 0x09 +#define WM8772_DACRATE 0x0a +#define WM8772_ADCRATE 0x0b +#define WM8772_ADCCTRL 0x0c +#define WM8772_RESET 0x1f + +#define WM8772_CACHE_REGNUM 10 + +#define WM8772_DACCLK 0 +#define WM8772_ADCCLK 1 + +#define WM8753_DAI_DAC 0 +#define WM8753_DAI_ADC 1 + +extern struct snd_soc_dai wm8772_dai[2]; +extern struct snd_soc_codec_device soc_codec_dev_wm8772; + +#endif diff --git a/sound/soc/codecs/wm8900.c b/sound/soc/codecs/wm8900.c index 6767de1..1e08d4f 100644 --- a/sound/soc/codecs/wm8900.c +++ b/sound/soc/codecs/wm8900.c @@ -517,22 +517,6 @@ SOC_SINGLE("LINEOUT2 LP -12dB", WM8900_REG_LOUTMIXCTL1, }; -/* add non dapm controls */ -static int wm8900_add_controls(struct snd_soc_codec *codec) -{ - int err, i; - - for (i = 0; i < ARRAY_SIZE(wm8900_snd_controls); i++) { - err = snd_ctl_add(codec->card, - snd_soc_cnew(&wm8900_snd_controls[i], - codec, NULL)); - if (err < 0) - return err; - } - - return 0; -} - static const struct snd_kcontrol_new wm8900_dapm_loutput2_control = SOC_DAPM_SINGLE("LINEOUT2L Switch", WM8900_REG_POWER3, 6, 1, 0); @@ -1439,7 +1423,8 @@ static int wm8900_probe(struct platform_device *pdev) goto pcm_err; } - wm8900_add_controls(codec); + snd_soc_add_controls(codec, wm8900_snd_controls, + ARRAY_SIZE(wm8900_snd_controls)); wm8900_add_widgets(codec); ret = snd_soc_init_card(socdev); diff --git a/sound/soc/codecs/wm8903.c b/sound/soc/codecs/wm8903.c index bde7454..6ff34b9 100644 --- a/sound/soc/codecs/wm8903.c +++ b/sound/soc/codecs/wm8903.c @@ -744,21 +744,6 @@ SOC_DOUBLE_R_TLV("Speaker Volume", 0, 63, 0, out_tlv), }; -static int wm8903_add_controls(struct snd_soc_codec *codec) -{ - int err, i; - - for (i = 0; i < ARRAY_SIZE(wm8903_snd_controls); i++) { - err = snd_ctl_add(codec->card, - snd_soc_cnew(&wm8903_snd_controls[i], - codec, NULL)); - if (err < 0) - return err; - } - - return 0; -} - static const struct snd_kcontrol_new linput_mode_mux = SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum); @@ -1737,7 +1722,8 @@ static int wm8903_probe(struct platform_device *pdev) goto err; } - wm8903_add_controls(socdev->codec); + snd_soc_add_controls(socdev->codec, wm8903_snd_controls, + ARRAY_SIZE(wm8903_snd_controls)); wm8903_add_widgets(socdev->codec); ret = snd_soc_init_card(socdev); diff --git a/sound/soc/codecs/wm8950.c b/sound/soc/codecs/wm8950.c new file mode 100644 index 0000000..4cabdf6 --- /dev/null +++ b/sound/soc/codecs/wm8950.c @@ -0,0 +1,745 @@ +/* + * wm8950.c -- WM8950 ALSA Soc Audio driver + * + * Copyright 2006 Wolfson Microelectronics PLC. + * + * Author: Liam Girdwood + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "wm8950.h" + +#define AUDIO_NAME "wm8950" +#define WM8950_VERSION "0.6" + +struct snd_soc_codec_device soc_codec_dev_wm8950; + +/* + * wm8950 register cache + * We can't read the WM8950 register space when we are + * using 2 wire for device control, so we cache them instead. + */ +static const u16 wm8950_reg[WM8950_CACHEREGNUM] = { + 0x0000, 0x0000, 0x0000, 0x0000, + 0x0050, 0x0000, 0x0140, 0x0000, + 0x0000, 0x0000, 0x0000, 0x00ff, + 0x0000, 0x0000, 0x0100, 0x00ff, + 0x0000, 0x0000, 0x012c, 0x002c, + 0x002c, 0x002c, 0x002c, 0x0000, + 0x0032, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, + 0x0038, 0x000b, 0x0032, 0x0000, + 0x0008, 0x000c, 0x0093, 0x00e9, + 0x0000, 0x0000, 0x0000, 0x0000, + 0x0003, 0x0010, 0x0000, 0x0000, + 0x0000, 0x0002, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0039, 0x0000, + 0x0000, +}; + +/* + * read wm8950 register cache + */ +static inline unsigned int wm8950_read_reg_cache(struct snd_soc_codec *codec, + unsigned int reg) +{ + u16 *cache = codec->reg_cache; + if (reg == WM8950_RESET) + return 0; + if (reg >= WM8950_CACHEREGNUM) + return -1; + return cache[reg]; +} + +/* + * write wm8950 register cache + */ +static inline void wm8950_write_reg_cache(struct snd_soc_codec *codec, + u16 reg, unsigned int value) +{ + u16 *cache = codec->reg_cache; + if (reg >= WM8950_CACHEREGNUM) + return; + cache[reg] = value; +} + +/* + * write to the WM8950 register space + */ +static int wm8950_write(struct snd_soc_codec *codec, unsigned int reg, + unsigned int value) +{ + u8 data[2]; + + /* data is + * D15..D9 WM8950 register offset + * D8...D0 register data + */ + data[0] = (reg << 1) | ((value >> 8) & 0x0001); + data[1] = value & 0x00ff; + + wm8950_write_reg_cache(codec, reg, value); + if (codec->hw_write(codec->control_data, data, 2) == 2) + return 0; + else + return -EIO; +} + +#define wm8950_reset(c) wm8950_write(c, WM8950_RESET, 0) + +static const char *wm8950_companding[] = {"Off", "NC", "u-law", "A-law" }; +static const char *wm8950_deemp[] = {"None", "32kHz", "44.1kHz", "48kHz" }; +static const char *wm8950_bw[] = {"Narrow", "Wide" }; +static const char *wm8950_eq1[] = {"80Hz", "105Hz", "135Hz", "175Hz" }; +static const char *wm8950_eq2[] = {"230Hz", "300Hz", "385Hz", "500Hz" }; +static const char *wm8950_eq3[] = {"650Hz", "850Hz", "1.1kHz", "1.4kHz" }; +static const char *wm8950_eq4[] = {"1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz" }; +static const char *wm8950_eq5[] = {"5.3kHz", "6.9kHz", "9kHz", "11.7kHz" }; +static const char *wm8950_alc[] = {"ALC", "Limiter" }; + +static const struct soc_enum wm8950_enum[] = { + SOC_ENUM_SINGLE(WM8950_COMP, 1, 4, wm8950_companding), /* adc */ + SOC_ENUM_SINGLE(WM8950_DAC, 4, 4, wm8950_deemp), + + SOC_ENUM_SINGLE(WM8950_EQ1, 5, 4, wm8950_eq1), + SOC_ENUM_SINGLE(WM8950_EQ2, 8, 2, wm8950_bw), + SOC_ENUM_SINGLE(WM8950_EQ2, 5, 4, wm8950_eq2), + SOC_ENUM_SINGLE(WM8950_EQ3, 8, 2, wm8950_bw), + + SOC_ENUM_SINGLE(WM8950_EQ3, 5, 4, wm8950_eq3), + SOC_ENUM_SINGLE(WM8950_EQ4, 8, 2, wm8950_bw), + SOC_ENUM_SINGLE(WM8950_EQ4, 5, 4, wm8950_eq4), + + SOC_ENUM_SINGLE(WM8950_EQ5, 5, 4, wm8950_eq5), + SOC_ENUM_SINGLE(WM8950_ALC3, 8, 2, wm8950_alc), +}; + +static const struct snd_kcontrol_new wm8950_snd_controls[] = { + +SOC_SINGLE("Digital Loopback Switch", WM8950_COMP, 0, 1, 0), + +SOC_ENUM("ADC Companding", wm8950_enum[0]), + +SOC_SINGLE("High Pass Filter Switch", WM8950_ADC, 8, 1, 0), +SOC_SINGLE("High Pass Cut Off", WM8950_ADC, 4, 7, 0), +SOC_SINGLE("ADC Inversion Switch", WM8950_COMP, 0, 1, 0), + +SOC_SINGLE("Capture Volume", WM8950_ADCVOL, 0, 127, 0), + +SOC_ENUM("Equaliser Function", wm8950_enum[3]), +SOC_ENUM("EQ1 Cut Off", wm8950_enum[4]), +SOC_SINGLE("EQ1 Volume", WM8950_EQ1, 0, 31, 1), + +SOC_ENUM("Equaliser EQ2 Bandwith", wm8950_enum[5]), +SOC_ENUM("EQ2 Cut Off", wm8950_enum[6]), +SOC_SINGLE("EQ2 Volume", WM8950_EQ2, 0, 31, 1), + +SOC_ENUM("Equaliser EQ3 Bandwith", wm8950_enum[7]), +SOC_ENUM("EQ3 Cut Off", wm8950_enum[8]), +SOC_SINGLE("EQ3 Volume", WM8950_EQ3, 0, 31, 1), + +SOC_ENUM("Equaliser EQ4 Bandwith", wm8950_enum[9]), +SOC_ENUM("EQ4 Cut Off", wm8950_enum[10]), +SOC_SINGLE("EQ4 Volume", WM8950_EQ4, 0, 31, 1), + +SOC_ENUM("EQ5 Cut Off", wm8950_enum[12]), +SOC_SINGLE("EQ5 Volume", WM8950_EQ5, 0, 31, 1), + +SOC_SINGLE("ALC Enable Switch", WM8950_ALC1, 8, 1, 0), +SOC_SINGLE("ALC Capture Max Gain", WM8950_ALC1, 3, 7, 0), +SOC_SINGLE("ALC Capture Min Gain", WM8950_ALC1, 0, 7, 0), + +SOC_SINGLE("ALC Capture ZC Switch", WM8950_ALC2, 8, 1, 0), +SOC_SINGLE("ALC Capture Hold", WM8950_ALC2, 4, 7, 0), +SOC_SINGLE("ALC Capture Target", WM8950_ALC2, 0, 15, 0), + +SOC_ENUM("ALC Capture Mode", wm8950_enum[13]), +SOC_SINGLE("ALC Capture Decay", WM8950_ALC3, 4, 15, 0), +SOC_SINGLE("ALC Capture Attack", WM8950_ALC3, 0, 15, 0), + +SOC_SINGLE("ALC Capture Noise Gate Switch", WM8950_NGATE, 3, 1, 0), +SOC_SINGLE("ALC Capture Noise Gate Threshold", WM8950_NGATE, 0, 7, 0), + +SOC_SINGLE("Capture PGA ZC Switch", WM8950_INPPGA, 7, 1, 0), +SOC_SINGLE("Capture PGA Volume", WM8950_INPPGA, 0, 63, 0), + +SOC_SINGLE("Capture Boost(+20dB)", WM8950_ADCBOOST, 8, 1, 0), +}; + +/* add non dapm controls */ +static int wm8950_add_controls(struct snd_soc_codec *codec) +{ + return snd_soc_add_controls(codec, wm8950_snd_controls, + ARRAY_SIZE(wm8950_snd_controls)); +} + +/* AUX Input boost vol */ +static const struct snd_kcontrol_new wm8950_aux_boost_controls = +SOC_DAPM_SINGLE("Aux Volume", WM8950_ADCBOOST, 0, 7, 0); + +/* Mic Input boost vol */ +static const struct snd_kcontrol_new wm8950_mic_boost_controls = +SOC_DAPM_SINGLE("Mic Volume", WM8950_ADCBOOST, 4, 7, 0); + +/* Capture boost switch */ +static const struct snd_kcontrol_new wm8950_capture_boost_controls = +SOC_DAPM_SINGLE("Capture Boost Switch", WM8950_INPPGA, 6, 1, 0); + +/* Aux In to PGA */ +static const struct snd_kcontrol_new wm8950_aux_capture_boost_controls = +SOC_DAPM_SINGLE("Aux Capture Boost Switch", WM8950_INPPGA, 2, 1, 0); + +/* Mic P In to PGA */ +static const struct snd_kcontrol_new wm8950_micp_capture_boost_controls = +SOC_DAPM_SINGLE("Mic P Capture Boost Switch", WM8950_INPPGA, 0, 1, 0); + +/* Mic N In to PGA */ +static const struct snd_kcontrol_new wm8950_micn_capture_boost_controls = +SOC_DAPM_SINGLE("Mic N Capture Boost Switch", WM8950_INPPGA, 1, 1, 0); + +static const struct snd_soc_dapm_widget wm8950_dapm_widgets[] = { +SND_SOC_DAPM_ADC("ADC", "HiFi Capture", WM8950_POWER3, 0, 0), +SND_SOC_DAPM_PGA("Aux Input", WM8950_POWER1, 6, 0, NULL, 0), +SND_SOC_DAPM_PGA("Mic PGA", WM8950_POWER2, 2, 0, NULL, 0), + +SND_SOC_DAPM_PGA("Aux Boost", SND_SOC_NOPM, 0, 0, + &wm8950_aux_boost_controls, 1), +SND_SOC_DAPM_PGA("Mic Boost", SND_SOC_NOPM, 0, 0, + &wm8950_mic_boost_controls, 1), +SND_SOC_DAPM_SWITCH("Capture Boost", SND_SOC_NOPM, 0, 0, + &wm8950_capture_boost_controls), + +SND_SOC_DAPM_MIXER("Boost Mixer", WM8950_POWER2, 4, 0, NULL, 0), + +SND_SOC_DAPM_MICBIAS("Mic Bias", WM8950_POWER1, 4, 0), + +SND_SOC_DAPM_INPUT("MICN"), +SND_SOC_DAPM_INPUT("MICP"), +SND_SOC_DAPM_INPUT("AUX"), +}; + +static const struct snd_soc_dapm_route audio_map[] = { + /* Boost Mixer */ + {"Boost Mixer", NULL, "ADC"}, + {"Capture Boost Switch", "Aux Capture Boost Switch", "AUX"}, + {"Aux Boost", "Aux Volume", "Boost Mixer"}, + {"Capture Boost", "Capture Switch", "Boost Mixer"}, + {"Mic Boost", "Mic Volume", "Boost Mixer"}, + + /* Inputs */ + {"MICP", NULL, "Mic Boost"}, + {"MICN", NULL, "Mic PGA"}, + {"Mic PGA", NULL, "Capture Boost"}, + {"AUX", NULL, "Aux Input"}, +}; + +static int wm8950_add_widgets(struct snd_soc_codec *codec) +{ + snd_soc_dapm_new_controls(codec, wm8950_dapm_widgets, + ARRAY_SIZE(wm8950_dapm_widgets)); + + snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + + snd_soc_dapm_new_widgets(codec); + return 0; +} + +struct pll_ { + unsigned int in_hz, out_hz; + unsigned int pre:4; /* prescale - 1 */ + unsigned int n:4; + unsigned int k; +}; + +static struct pll_ pll[] = { + {12000000, 11289600, 0, 7, 0x86c220}, + {12000000, 12288000, 0, 8, 0x3126e8}, + {13000000, 11289600, 0, 6, 0xf28bd4}, + {13000000, 12288000, 0, 7, 0x8fd525}, + {12288000, 11289600, 0, 7, 0x59999a}, + {11289600, 12288000, 0, 8, 0x80dee9}, + /* liam - add more entries */ +}; + +static int wm8950_set_dai_pll(struct snd_soc_dai *codec_dai, + int pll_id, unsigned int freq_in, unsigned int freq_out) +{ + struct snd_soc_codec *codec = codec_dai->codec; + int i; + u16 reg; + + if (freq_in == 0 || freq_out == 0) { + reg = wm8950_read_reg_cache(codec, WM8950_POWER1); + wm8950_write(codec, WM8950_POWER1, reg & 0x1df); + return 0; + } + + for (i = 0; i < ARRAY_SIZE(pll); i++) { + if (freq_in == pll[i].in_hz && freq_out == pll[i].out_hz) { + wm8950_write(codec, WM8950_PLLN, + (pll[i].pre << 4) | pll[i].n); + wm8950_write(codec, WM8950_PLLK1, pll[i].k >> 18); + wm8950_write(codec, WM8950_PLLK1, + (pll[i].k >> 9) && 0x1ff); + wm8950_write(codec, WM8950_PLLK1, pll[i].k && 0x1ff); + reg = wm8950_read_reg_cache(codec, WM8950_POWER1); + wm8950_write(codec, WM8950_POWER1, reg | 0x020); + return 0; + } + } + return -EINVAL; +} + +/* + * Configure WM8950 clock dividers. + */ +static int wm8950_set_dai_clkdiv(struct snd_soc_dai *codec_dai, + int div_id, int div) +{ + struct snd_soc_codec *codec = codec_dai->codec; + u16 reg; + + switch (div_id) { + case WM8950_OPCLKDIV: + reg = wm8950_read_reg_cache(codec, WM8950_GPIO & 0x1cf); + wm8950_write(codec, WM8950_GPIO, reg | div); + break; + case WM8950_MCLKDIV: + reg = wm8950_read_reg_cache(codec, WM8950_CLOCK & 0x1f); + wm8950_write(codec, WM8950_CLOCK, reg | div); + break; + case WM8950_ADCCLK: + reg = wm8950_read_reg_cache(codec, WM8950_ADC & 0x1f7); + wm8950_write(codec, WM8950_ADC, reg | div); + break; + case WM8950_BCLKDIV: + reg = wm8950_read_reg_cache(codec, WM8950_CLOCK & 0x1e3); + wm8950_write(codec, WM8950_CLOCK, reg | div); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int wm8950_set_dai_fmt(struct snd_soc_dai *codec_dai, + unsigned int fmt) +{ + struct snd_soc_codec *codec = codec_dai->codec; + u16 iface = 0; + u16 clk = wm8950_read_reg_cache(codec, WM8950_CLOCK) & 0x1fe; + + /* set master/slave audio interface */ + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + clk |= 0x0001; + break; + case SND_SOC_DAIFMT_CBS_CFS: + break; + default: + return -EINVAL; + } + + /* interface format */ + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + iface |= 0x0010; + break; + case SND_SOC_DAIFMT_RIGHT_J: + break; + case SND_SOC_DAIFMT_LEFT_J: + iface |= 0x0008; + break; + case SND_SOC_DAIFMT_DSP_A: + iface |= 0x00018; + break; + default: + return -EINVAL; + } + + /* clock inversion */ + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + case SND_SOC_DAIFMT_IB_IF: + iface |= 0x0180; + break; + case SND_SOC_DAIFMT_IB_NF: + iface |= 0x0100; + break; + case SND_SOC_DAIFMT_NB_IF: + iface |= 0x0080; + break; + default: + return -EINVAL; + } + + wm8950_write(codec, WM8950_IFACE, iface); + wm8950_write(codec, WM8950_CLOCK, clk); + return 0; +} + +static int wm8950_pcm_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->codec; + u16 iface = wm8950_read_reg_cache(codec, WM8950_IFACE) & 0x19f; + u16 adn = wm8950_read_reg_cache(codec, WM8950_ADD) & 0x1f1; + + /* bit size */ + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + break; + case SNDRV_PCM_FORMAT_S20_3LE: + iface |= 0x0020; + break; + case SNDRV_PCM_FORMAT_S24_LE: + iface |= 0x0040; + break; + case SNDRV_PCM_FORMAT_S32_LE: + iface |= 0x0060; + break; + } + + /* filter coefficient */ + switch (params_rate(params)) { + case SNDRV_PCM_RATE_8000: + adn |= 0x5 << 1; + break; + case SNDRV_PCM_RATE_11025: + adn |= 0x4 << 1; + break; + case SNDRV_PCM_RATE_16000: + adn |= 0x3 << 1; + break; + case SNDRV_PCM_RATE_22050: + adn |= 0x2 << 1; + break; + case SNDRV_PCM_RATE_32000: + adn |= 0x1 << 1; + break; + case SNDRV_PCM_RATE_44100: + break; + } + + wm8950_write(codec, WM8950_IFACE, iface); + wm8950_write(codec, WM8950_ADD, adn); + return 0; +} + +/* liam need to make this lower power with dapm */ +static int wm8950_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level) +{ + switch (level) { + case SND_SOC_BIAS_ON: + wm8950_write(codec, WM8950_POWER1, 0x1ff); + wm8950_write(codec, WM8950_POWER2, 0x1ff); + wm8950_write(codec, WM8950_POWER3, 0x1ff); + break; + case SND_SOC_BIAS_PREPARE: + case SND_SOC_BIAS_STANDBY: + break; + case SND_SOC_BIAS_OFF: + /* everything off, dac mute, inactive */ + wm8950_write(codec, WM8950_POWER1, 0x0); + wm8950_write(codec, WM8950_POWER2, 0x0); + wm8950_write(codec, WM8950_POWER3, 0x0); + break; + } + codec->bias_level = level; + return 0; +} + +#define WM8950_RATES (SNDRV_PCM_RATE_8000_48000) + +#define WM8950_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ + SNDRV_PCM_FMTBIT_S24_LE) + +struct snd_soc_dai wm8950_dai = { + .name = "WM8950 HiFi", + .capture = { + .stream_name = "Capture", + .channels_min = 1, + .channels_max = 1, + .rates = WM8950_RATES, + .formats = WM8950_FORMATS,}, + .ops = { + .hw_params = wm8950_pcm_hw_params, + .set_fmt = wm8950_set_dai_fmt, + .set_clkdiv = wm8950_set_dai_clkdiv, + .set_pll = wm8950_set_dai_pll, + }, +}; +EXPORT_SYMBOL_GPL(wm8950_dai); + +static int wm8950_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + + wm8950_set_bias_level(codec, SND_SOC_BIAS_OFF); + return 0; +} + +static int wm8950_resume(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + int i; + u8 data[2]; + u16 *cache = codec->reg_cache; + + /* Sync reg_cache with the hardware */ + for (i = 0; i < ARRAY_SIZE(wm8950_reg); i++) { + data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001); + data[1] = cache[i] & 0x00ff; + codec->hw_write(codec->control_data, data, 2); + } + wm8950_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + wm8950_set_bias_level(codec, codec->suspend_bias_level); + return 0; +} + +/* + * initialise the WM8950 driver + * register the mixer and dsp interfaces with the kernel + */ +static int wm8950_init(struct snd_soc_device *socdev) +{ + struct snd_soc_codec *codec = socdev->codec; + int ret = 0; + + codec->name = "WM8950"; + codec->owner = THIS_MODULE; + codec->read = wm8950_read_reg_cache; + codec->write = wm8950_write; + codec->set_bias_level = wm8950_set_bias_level; + codec->dai = &wm8950_dai; + codec->num_dai = 1; + codec->reg_cache_size = ARRAY_SIZE(wm8950_reg); + codec->reg_cache = kmemdup(wm8950_reg, sizeof(wm8950_reg), GFP_KERNEL); + + if (codec->reg_cache == NULL) + return -ENOMEM; + + wm8950_reset(codec); + + /* register pcms */ + ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); + if (ret < 0) { + pr_err("wm8950: failed to create pcms\n"); + goto pcm_err; + } + + /* power on device */ + wm8950_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + wm8950_add_controls(codec); + wm8950_add_widgets(codec); + ret = snd_soc_init_card(socdev); + if (ret < 0) { + pr_err("wm8950: failed to register card\n"); + goto card_err; + } + return ret; + +card_err: + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); +pcm_err: + kfree(codec->reg_cache); + return ret; +} + +static struct snd_soc_device *wm8950_socdev; + +#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE) + +/* + * WM8950 2 wire address is 0x1a + */ +#define I2C_DRIVERID_WM8950 0xfefe /* liam - need a proper id */ + +static unsigned short normal_i2c[] = { 0, I2C_CLIENT_END }; + +/* Magic definition of all other variables and things */ +I2C_CLIENT_INSMOD; + +static struct i2c_driver wm8950_i2c_driver; +static struct i2c_client client_template; + +/* If the i2c layer weren't so broken, we could pass this kind of data + around */ + +static int wm8950_codec_probe(struct i2c_adapter *adap, int addr, int kind) +{ + struct snd_soc_device *socdev = wm8950_socdev; + struct wm8950_setup_data *setup = socdev->codec_data; + struct snd_soc_codec *codec = socdev->codec; + struct i2c_client *i2c; + int ret; + + if (addr != setup->i2c_address) + return -ENODEV; + + client_template.adapter = adap; + client_template.addr = addr; + + i2c = kmemdup(&client_template, sizeof(client_template), GFP_KERNEL); + if (i2c == NULL) { + kfree(codec); + return -ENOMEM; + } + i2c_set_clientdata(i2c, codec); + codec->control_data = i2c; + + ret = i2c_attach_client(i2c); + if (ret < 0) { + pr_err("failed to attach codec at addr %x\n", addr); + goto err; + } + + ret = wm8950_init(socdev); + if (ret < 0) { + pr_err("failed to initialise WM8950\n"); + goto err; + } + return ret; + +err: + kfree(codec); + kfree(i2c); + return ret; +} + +static int wm8950_i2c_detach(struct i2c_client *client) +{ + struct snd_soc_codec *codec = i2c_get_clientdata(client); + i2c_detach_client(client); + kfree(codec->reg_cache); + kfree(client); + return 0; +} + +static int wm8950_i2c_attach(struct i2c_adapter *adap) +{ + return i2c_probe(adap, &addr_data, wm8950_codec_probe); +} + +/* corgi i2c codec control layer */ +static struct i2c_driver wm8950_i2c_driver = { + .driver = { + .name = "WM8950 I2C Codec", + .owner = THIS_MODULE, + }, + .id = I2C_DRIVERID_WM8950, + .attach_adapter = wm8950_i2c_attach, + .detach_client = wm8950_i2c_detach, + .command = NULL, +}; + +static struct i2c_client client_template = { + .name = "WM8950", + .driver = &wm8950_i2c_driver, +}; +#endif + +static int wm8950_probe(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct wm8950_setup_data *setup; + struct snd_soc_codec *codec; + int ret = 0; + + pr_info("WM8950 Audio Codec %s", WM8950_VERSION); + + setup = socdev->codec_data; + codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); + if (codec == NULL) + return -ENOMEM; + + socdev->codec = codec; + mutex_init(&codec->mutex); + INIT_LIST_HEAD(&codec->dapm_widgets); + INIT_LIST_HEAD(&codec->dapm_paths); + + wm8950_socdev = socdev; +#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE) + if (setup->i2c_address) { + normal_i2c[0] = setup->i2c_address; + codec->hw_write = (hw_write_t)i2c_master_send; + ret = i2c_add_driver(&wm8950_i2c_driver); + if (ret != 0) + printk(KERN_ERR "can't add i2c driver"); + } +#else + /* Add other interfaces here */ +#endif + return ret; +} + +/* power down chip */ +static int wm8950_remove(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + + if (codec->control_data) + wm8950_set_bias_level(codec, SND_SOC_BIAS_OFF); + + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); +#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) + i2c_del_driver(&wm8950_i2c_driver); +#endif + kfree(codec); + + return 0; +} + +struct snd_soc_codec_device soc_codec_dev_wm8950 = { + .probe = wm8950_probe, + .remove = wm8950_remove, + .suspend = wm8950_suspend, + .resume = wm8950_resume, +}; +EXPORT_SYMBOL_GPL(soc_codec_dev_wm8950); + +static int __init wm8950_modinit(void) +{ + return snd_soc_register_dai(&wm8950_dai); +} +module_init(wm8950_modinit); + +static void __exit wm8950_exit(void) +{ + snd_soc_unregister_dai(&wm8950_dai); +} +module_exit(wm8950_exit); + +MODULE_DESCRIPTION("ASoC WM8950 driver"); +MODULE_AUTHOR("Liam Girdwood"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/wm8950.h b/sound/soc/codecs/wm8950.h new file mode 100644 index 0000000..88c74a9 --- /dev/null +++ b/sound/soc/codecs/wm8950.h @@ -0,0 +1,93 @@ +/* + * wm8950.h -- WM8950 Soc Audio driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _WM8950_H +#define _WM8950_H + +/* WM8950 register space */ + +#define WM8950_RESET 0x0 +#define WM8950_POWER1 0x1 +#define WM8950_POWER2 0x2 +#define WM8950_POWER3 0x3 +#define WM8950_IFACE 0x4 +#define WM8950_COMP 0x5 +#define WM8950_CLOCK 0x6 +#define WM8950_ADD 0x7 +#define WM8950_GPIO 0x8 +#define WM8950_DAC 0xa +#define WM8950_ADC 0xe +#define WM8950_ADCVOL 0xf +#define WM8950_EQ1 0x12 +#define WM8950_EQ2 0x13 +#define WM8950_EQ3 0x14 +#define WM8950_EQ4 0x15 +#define WM8950_EQ5 0x16 +#define WM8950_NOTCH1 0x1b +#define WM8950_NOTCH2 0x1c +#define WM8950_NOTCH3 0x1d +#define WM8950_NOTCH4 0x1e +#define WM8950_ALC1 0x20 +#define WM8950_ALC2 0x21 +#define WM8950_ALC3 0x22 +#define WM8950_NGATE 0x23 +#define WM8950_PLLN 0x24 +#define WM8950_PLLK1 0x25 +#define WM8950_PLLK2 0x26 +#define WM8950_PLLK3 0x27 +#define WM8950_INPUT 0x2c +#define WM8950_INPPGA 0x2d +#define WM8950_ADCBOOST 0x2f +#define WM8950_OUTPUT 0x31 + +#define WM8950_CACHEREGNUM 57 + +/* Clock divider Id's */ +#define WM8950_OPCLKDIV 0 +#define WM8950_MCLKDIV 1 +#define WM8950_ADCCLK 2 +#define WM8950_BCLKDIV 3 + + +/* ADC clock dividers */ +#define WM8950_ADCCLK_F2 (1 << 3) +#define WM8950_ADCCLK_F4 (0 << 3) + +/* PLL Out dividers */ +#define WM8950_OPCLKDIV_1 (0 << 4) +#define WM8950_OPCLKDIV_2 (1 << 4) +#define WM8950_OPCLKDIV_3 (2 << 4) +#define WM8950_OPCLKDIV_4 (3 << 4) + +/* BCLK clock dividers */ +#define WM8950_BCLKDIV_1 (0 << 2) +#define WM8950_BCLKDIV_2 (1 << 2) +#define WM8950_BCLKDIV_4 (2 << 2) +#define WM8950_BCLKDIV_8 (3 << 2) +#define WM8950_BCLKDIV_16 (4 << 2) +#define WM8950_BCLKDIV_32 (5 << 2) + +/* MCLK clock dividers */ +#define WM8950_MCLKDIV_1 (0 << 5) +#define WM8950_MCLKDIV_1_5 (1 << 5) +#define WM8950_MCLKDIV_2 (2 << 5) +#define WM8950_MCLKDIV_3 (3 << 5) +#define WM8950_MCLKDIV_4 (4 << 5) +#define WM8950_MCLKDIV_6 (5 << 5) +#define WM8950_MCLKDIV_8 (6 << 5) +#define WM8950_MCLKDIV_12 (7 << 5) + + +struct wm8950_setup_data { + unsigned short i2c_address; +}; + +extern struct snd_soc_dai wm8950_dai; +extern struct snd_soc_codec_device soc_codec_dev_wm8950; + +#endif diff --git a/sound/soc/codecs/wm8951.c b/sound/soc/codecs/wm8951.c new file mode 100644 index 0000000..b721609 --- /dev/null +++ b/sound/soc/codecs/wm8951.c @@ -0,0 +1,680 @@ +/* + * wm8951.c -- WM8951 ALSA SoC Audio driver + * + * Copyright 2005 Openedhand Ltd. + * + * Author: Richard Purdie + * + * Based on wm8753.c by Liam Girdwood + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "wm8951.h" + +#define AUDIO_NAME "wm8951" +#define WM8951_VERSION "0.1" + +struct snd_soc_codec_device soc_codec_dev_wm8951; + +/* codec private data */ +struct wm8951_priv { + unsigned int sysclk; +}; + +/* + * wm8951 register cache + * We can't read the WM8951 register space when we are + * using 2 wire for device control, so we cache them instead. + * There is no point in caching the reset register + */ +static const u16 wm8951_reg[WM8951_CACHEREGNUM] = { + 0x0097, 0x0097, 0x0079, 0x0079, + 0x000a, 0x0008, 0x009f, 0x000a, + 0x0000, 0x0000 +}; + +/* + * read wm8951 register cache + */ +static inline unsigned int wm8951_read_reg_cache(struct snd_soc_codec *codec, + unsigned int reg) +{ + u16 *cache = codec->reg_cache; + if (reg == WM8951_RESET) + return 0; + if (reg >= WM8951_CACHEREGNUM) + return -1; + return cache[reg]; +} + +/* + * write wm8951 register cache + */ +static inline void wm8951_write_reg_cache(struct snd_soc_codec *codec, + u16 reg, unsigned int value) +{ + u16 *cache = codec->reg_cache; + if (reg >= WM8951_CACHEREGNUM) + return; + cache[reg] = value; +} + +/* + * write to the WM8951 register space + */ +static int wm8951_write(struct snd_soc_codec *codec, unsigned int reg, + unsigned int value) +{ + u8 data[2]; + + /* data is + * D15..D9 WM8951 register offset + * D8...D0 register data + */ + data[0] = (reg << 1) | ((value >> 8) & 0x0001); + data[1] = value & 0x00ff; + + wm8951_write_reg_cache (codec, reg, value); + if (codec->hw_write(codec->control_data, data, 2) == 2) + return 0; + else + return -EIO; +} + +#define wm8951_reset(c) wm8951_write(c, WM8951_RESET, 0) + +static const char *wm8951_input_select[] = {"Line In", "Mic"}; +static const char *wm8951_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"}; + +static const struct soc_enum wm8951_enum[] = { + SOC_ENUM_SINGLE(WM8951_APANA, 2, 2, wm8951_input_select), + SOC_ENUM_SINGLE(WM8951_APDIGI, 1, 4, wm8951_deemph), +}; + +static const struct snd_kcontrol_new wm8951_snd_controls[] = { + +SOC_DOUBLE_R("Capture Volume", WM8951_LINVOL, WM8951_RINVOL, 0, 31, 0), +SOC_DOUBLE_R("Line Capture Switch", WM8951_LINVOL, WM8951_RINVOL, 7, 1, 1), + +SOC_SINGLE("Mic Boost (+20dB)", WM8951_APANA, 0, 1, 0), +SOC_SINGLE("Capture Mic Switch", WM8951_APANA, 1, 1, 1), + +SOC_SINGLE("ADC High Pass Filter Switch", WM8951_APDIGI, 0, 1, 1), +SOC_SINGLE("Store DC Offset Switch", WM8951_APDIGI, 4, 1, 0), +}; + +/* add non dapm controls */ +static int wm8951_add_controls(struct snd_soc_codec *codec) +{ + int err, i; + + for (i = 0; i < ARRAY_SIZE(wm8951_snd_controls); i++) { + if ((err = snd_ctl_add(codec->card, + snd_soc_cnew(&wm8951_snd_controls[i],codec, NULL))) < 0) + return err; + } + + return 0; +} + +/* Input mux */ +static const struct snd_kcontrol_new wm8951_input_mux_controls = +SOC_DAPM_ENUM("Input Select", wm8951_enum[0]); + +static const struct snd_soc_dapm_widget wm8951_dapm_widgets[] = { +SND_SOC_DAPM_ADC("ADC", "HiFi Capture", WM8951_PWR, 2, 1), +SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 0, 0, &wm8951_input_mux_controls), +SND_SOC_DAPM_PGA("Line Input", WM8951_PWR, 0, 1, NULL, 0), +SND_SOC_DAPM_MICBIAS("Mic Bias", WM8951_PWR, 1, 1), +SND_SOC_DAPM_INPUT("MICIN"), +SND_SOC_DAPM_INPUT("RLINEIN"), +SND_SOC_DAPM_INPUT("LLINEIN"), +}; + +static const struct snd_soc_dapm_route intercon[] = { + /* input mux */ + {"Input Mux", "Line In", "Line Input"}, + {"Input Mux", "Mic", "Mic Bias"}, + {"ADC", NULL, "Input Mux"}, + + /* inputs */ + {"Line Input", NULL, "LLINEIN"}, + {"Line Input", NULL, "RLINEIN"}, + {"Mic Bias", NULL, "MICIN"}, +}; + +static int wm8951_add_widgets(struct snd_soc_codec *codec) +{ + snd_soc_dapm_new_controls(codec, wm8951_dapm_widgets, + ARRAY_SIZE(wm8951_dapm_widgets)); + + /* set up audio path interconnects */ + snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); + + snd_soc_dapm_new_widgets(codec); + return 0; +} + +struct _coeff_div { + u32 mclk; + u32 rate; + u16 fs; + u8 sr:4; + u8 bosr:1; + u8 usb:1; +}; + +/* codec mclk clock divider coefficients */ +static const struct _coeff_div coeff_div[] = { + /* 48k */ + {12288000, 48000, 256, 0x0, 0x0, 0x0}, + {18432000, 48000, 384, 0x0, 0x1, 0x0}, + {12000000, 48000, 250, 0x0, 0x0, 0x1}, + + /* 32k */ + {12288000, 32000, 384, 0x6, 0x0, 0x0}, + {18432000, 32000, 576, 0x6, 0x1, 0x0}, + {12000000, 32000, 375, 0x6, 0x0, 0x1}, + + /* 8k */ + {12288000, 8000, 1536, 0x3, 0x0, 0x0}, + {18432000, 8000, 2304, 0x3, 0x1, 0x0}, + {11289600, 8000, 1408, 0xb, 0x0, 0x0}, + {16934400, 8000, 2112, 0xb, 0x1, 0x0}, + {12000000, 8000, 1500, 0x3, 0x0, 0x1}, + + /* 96k */ + {12288000, 96000, 128, 0x7, 0x0, 0x0}, + {18432000, 96000, 192, 0x7, 0x1, 0x0}, + {12000000, 96000, 125, 0x7, 0x0, 0x1}, + + /* 44.1k */ + {11289600, 44100, 256, 0x8, 0x0, 0x0}, + {16934400, 44100, 384, 0x8, 0x1, 0x0}, + {12000000, 44100, 272, 0x8, 0x1, 0x1}, + + /* 88.2k */ + {11289600, 88200, 128, 0xf, 0x0, 0x0}, + {16934400, 88200, 192, 0xf, 0x1, 0x0}, + {12000000, 88200, 136, 0xf, 0x1, 0x1}, +}; + +static inline int get_coeff(int mclk, int rate) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(coeff_div); i++) { + if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk) + return i; + } + return 0; +} + +static int wm8951_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->codec; + struct wm8951_priv *wm8951 = codec->private_data; + u16 iface = wm8951_read_reg_cache(codec, WM8951_IFACE) & 0xfff3; + int i = get_coeff(wm8951->sysclk, params_rate(params)); + u16 srate = (coeff_div[i].sr << 2) | + (coeff_div[i].bosr << 1) | coeff_div[i].usb; + + wm8951_write(codec, WM8951_SRATE, srate); + + /* bit size */ + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + break; + case SNDRV_PCM_FORMAT_S20_3LE: + iface |= 0x0004; + break; + case SNDRV_PCM_FORMAT_S24_LE: + iface |= 0x0008; + break; + } + + wm8951_write(codec, WM8951_IFACE, iface); + return 0; +} + +static int wm8951_pcm_prepare(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->codec; + + /* set active */ + wm8951_write(codec, WM8951_ACTIVE, 0x0001); + + return 0; +} + +static void wm8951_shutdown(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->codec; + + /* deactivate */ + if (!codec->active) { + udelay(50); + wm8951_write(codec, WM8951_ACTIVE, 0x0); + } +} + +static int wm8951_mute(struct snd_soc_dai *dai, int mute) +{ + struct snd_soc_codec *codec = dai->codec; + u16 mute_reg = wm8951_read_reg_cache(codec, WM8951_APDIGI) & 0xfff7; + + if (mute) + wm8951_write(codec, WM8951_APDIGI, mute_reg | 0x8); + else + wm8951_write(codec, WM8951_APDIGI, mute_reg); + return 0; +} + +static int wm8951_set_dai_sysclk(struct snd_soc_dai *codec_dai, + int clk_id, unsigned int freq, int dir) +{ + struct snd_soc_codec *codec = codec_dai->codec; + struct wm8951_priv *wm8951 = codec->private_data; + + switch (freq) { + case 11289600: + case 12000000: + case 12288000: + case 16934400: + case 18432000: + wm8951->sysclk = freq; + return 0; + } + return -EINVAL; +} + + +static int wm8951_set_dai_fmt(struct snd_soc_dai *codec_dai, + unsigned int fmt) +{ + struct snd_soc_codec *codec = codec_dai->codec; + u16 iface = 0; + + /* set master/slave audio interface */ + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + iface |= 0x0040; + break; + case SND_SOC_DAIFMT_CBS_CFS: + break; + default: + return -EINVAL; + } + + /* interface format */ + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + iface |= 0x0002; + break; + case SND_SOC_DAIFMT_RIGHT_J: + break; + case SND_SOC_DAIFMT_LEFT_J: + iface |= 0x0001; + break; + case SND_SOC_DAIFMT_DSP_A: + iface |= 0x0003; + break; + case SND_SOC_DAIFMT_DSP_B: + iface |= 0x0013; + break; + default: + return -EINVAL; + } + + /* clock inversion */ + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + case SND_SOC_DAIFMT_IB_IF: + iface |= 0x0090; + break; + case SND_SOC_DAIFMT_IB_NF: + iface |= 0x0080; + break; + case SND_SOC_DAIFMT_NB_IF: + iface |= 0x0010; + break; + default: + return -EINVAL; + } + + /* set iface */ + wm8951_write(codec, WM8951_IFACE, iface); + return 0; +} + +static int wm8951_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level) +{ + u16 reg = wm8951_read_reg_cache(codec, WM8951_PWR) & 0xff7f; + + switch (level) { + case SND_SOC_BIAS_ON: + wm8951_write(codec, WM8951_PWR, reg); + break; + case SND_SOC_BIAS_PREPARE: + break; + case SND_SOC_BIAS_STANDBY: + wm8951_write(codec, WM8951_PWR, reg | 0x0040); + break; + case SND_SOC_BIAS_OFF: + wm8951_write(codec, WM8951_ACTIVE, 0x0); + wm8951_write(codec, WM8951_PWR, 0xffff); + break; + } + codec->suspend_bias_level = level; + return 0; +} + +#define WM8951_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ + SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\ + SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\ + SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |\ + SNDRV_PCM_RATE_96000) + +#define WM8951_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ + SNDRV_PCM_FMTBIT_S24_LE) + +struct snd_soc_dai wm8951_dai = { + .name = "WM8951", + .capture = { + .stream_name = "Capture", + .channels_min = 1, + .channels_max = 2, + .rates = WM8951_RATES, + .formats = WM8951_FORMATS,}, + .ops = { + .prepare = wm8951_pcm_prepare, + .hw_params = wm8951_hw_params, + .shutdown = wm8951_shutdown, + }, + .dai_ops = { + .digital_mute = wm8951_mute, + .set_sysclk = wm8951_set_dai_sysclk, + .set_fmt = wm8951_set_dai_fmt, + } +}; +EXPORT_SYMBOL_GPL(wm8951_dai); + +static int wm8951_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + + wm8951_write(codec, WM8951_ACTIVE, 0x0); + wm8951_set_bias_level(codec, SND_SOC_BIAS_OFF); + return 0; +} + +static int wm8951_resume(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + int i; + u8 data[2]; + u16 *cache = codec->reg_cache; + + /* Sync reg_cache with the hardware */ + for (i = 0; i < ARRAY_SIZE(wm8951_reg); i++) { + data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001); + data[1] = cache[i] & 0x00ff; + codec->hw_write(codec->control_data, data, 2); + } + wm8951_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + wm8951_set_bias_level(codec, codec->suspend_bias_level); + return 0; +} + +/* + * initialise the WM8951 driver + * register the mixer and dsp interfaces with the kernel + */ +static int wm8951_init(struct snd_soc_device *socdev) +{ + struct snd_soc_codec *codec = socdev->codec; + int reg, ret = 0; + + codec->name = "WM8951"; + codec->owner = THIS_MODULE; + codec->read = wm8951_read_reg_cache; + codec->write = wm8951_write; + codec->set_bias_level = wm8951_set_bias_level; + codec->dai = &wm8951_dai; + codec->num_dai = 1; + codec->reg_cache_size = ARRAY_SIZE(wm8951_reg); + codec->reg_cache = kmemdup(wm8951_reg, sizeof(wm8951_reg), GFP_KERNEL); + if (codec->reg_cache == NULL) + return -ENOMEM; + + wm8951_reset(codec); + + /* register pcms */ + ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); + if (ret < 0) { + printk(KERN_ERR "wm8951: failed to create pcms\n"); + goto pcm_err; + } + + /* power on device */ + wm8951_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + + /* set the update bits */ + reg = wm8951_read_reg_cache(codec, WM8951_LINVOL); + wm8951_write(codec, WM8951_LINVOL, reg | 0x0100); + reg = wm8951_read_reg_cache(codec, WM8951_RINVOL); + wm8951_write(codec, WM8951_RINVOL, reg | 0x0100); + + wm8951_add_controls(codec); + wm8951_add_widgets(codec); + ret = snd_soc_register_card(socdev); + if (ret < 0) { + printk(KERN_ERR "wm8951: failed to register card\n"); + goto card_err; + } + + return ret; + +card_err: + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); +pcm_err: + kfree(codec->reg_cache); + return ret; +} + +static struct snd_soc_device *wm8951_socdev; + +#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE) + +/* + * WM8951 2 wire address is determined by GPIO5 + * state during powerup. + * low = 0x1a + * high = 0x1b + */ +static unsigned short normal_i2c[] = { 0, I2C_CLIENT_END }; + +/* Magic definition of all other variables and things */ +I2C_CLIENT_INSMOD; + +static struct i2c_driver wm8951_i2c_driver; +static struct i2c_client client_template; + +/* If the i2c layer weren't so broken, we could pass this kind of data + around */ + +static int wm8951_codec_probe(struct i2c_adapter *adap, int addr, int kind) +{ + struct snd_soc_device *socdev = wm8951_socdev; + struct wm8951_setup_data *setup = socdev->codec_data; + struct snd_soc_codec *codec = socdev->codec; + struct i2c_client *i2c; + int ret; + + if (addr != setup->i2c_address) + return -ENODEV; + + client_template.adapter = adap; + client_template.addr = addr; + + i2c = kmemdup(&client_template, sizeof(client_template), GFP_KERNEL); + if (i2c == NULL) { + kfree(codec); + return -ENOMEM; + } + i2c_set_clientdata(i2c, codec); + codec->control_data = i2c; + + ret = i2c_attach_client(i2c); + if (ret < 0) { + pr_err("failed to attach codec at addr %x\n", addr); + goto err; + } + + ret = wm8951_init(socdev); + if (ret < 0) { + pr_err("failed to initialise WM8951\n"); + goto err; + } + return ret; + +err: + kfree(codec); + kfree(i2c); + return ret; +} + +static int wm8951_i2c_detach(struct i2c_client *client) +{ + struct snd_soc_codec* codec = i2c_get_clientdata(client); + i2c_detach_client(client); + kfree(codec->reg_cache); + kfree(client); + return 0; +} + +static int wm8951_i2c_attach(struct i2c_adapter *adap) +{ + return i2c_probe(adap, &addr_data, wm8951_codec_probe); +} + +/* corgi i2c codec control layer */ +static struct i2c_driver wm8951_i2c_driver = { + .driver = { + .name = "WM8951 I2C Codec", + .owner = THIS_MODULE, + }, + .attach_adapter = wm8951_i2c_attach, + .detach_client = wm8951_i2c_detach, + .command = NULL, +}; + +static struct i2c_client client_template = { + .name = "WM8951", + .driver = &wm8951_i2c_driver, +}; +#endif + +static int wm8951_probe(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct wm8951_setup_data *setup; + struct snd_soc_codec *codec; + struct wm8951_priv *wm8951; + int ret = 0; + + pr_info("WM8951 Audio Codec %s", WM8951_VERSION); + + setup = socdev->codec_data; + codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); + if (codec == NULL) + return -ENOMEM; + + wm8951 = kzalloc(sizeof(struct wm8951_priv), GFP_KERNEL); + if (wm8951 == NULL) { + kfree(codec); + return -ENOMEM; + } + + codec->private_data = wm8951; + socdev->codec = codec; + mutex_init(&codec->mutex); + INIT_LIST_HEAD(&codec->dapm_widgets); + INIT_LIST_HEAD(&codec->dapm_paths); + + wm8951_socdev = socdev; +#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE) + if (setup->i2c_address) { + normal_i2c[0] = setup->i2c_address; + codec->hw_write = (hw_write_t)i2c_master_send; + ret = i2c_add_driver(&wm8951_i2c_driver); + if (ret != 0) + printk(KERN_ERR "can't add i2c driver"); + } +#else + /* Add other interfaces here */ +#endif + return ret; +} + +/* power down chip */ +static int wm8951_remove(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + + if (codec->control_data) + wm8951_set_bias_level(codec, SND_SOC_BIAS_OFF); + + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); +#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE) + i2c_del_driver(&wm8951_i2c_driver); +#endif + kfree(codec->private_data); + kfree(codec); + + return 0; +} + +struct snd_soc_codec_device soc_codec_dev_wm8951 = { + .probe = wm8951_probe, + .remove = wm8951_remove, + .suspend = wm8951_suspend, + .resume = wm8951_resume, +}; + +EXPORT_SYMBOL_GPL(soc_codec_dev_wm8951); + +MODULE_DESCRIPTION("ASoC WM8951 driver"); +MODULE_AUTHOR("Richard Purdie"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/wm8951.h b/sound/soc/codecs/wm8951.h new file mode 100644 index 0000000..2260cdc --- /dev/null +++ b/sound/soc/codecs/wm8951.h @@ -0,0 +1,42 @@ +/* + * wm8951.h -- WM8951 Soc Audio driver + * + * Copyright 2005 Openedhand Ltd. + * + * Author: Richard Purdie + * + * Based on wm8753.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _WM8951_H +#define _WM8951_H + +/* WM8951 register space */ + +#define WM8951_LINVOL 0x00 +#define WM8951_RINVOL 0x01 +#define WM8951_APANA 0x04 +#define WM8951_APDIGI 0x05 +#define WM8951_PWR 0x06 +#define WM8951_IFACE 0x07 +#define WM8951_SRATE 0x08 +#define WM8951_ACTIVE 0x09 +#define WM8951_RESET 0x0f + +#define WM8951_CACHEREGNUM 10 + +#define WM8951_SYSCLK 0 +#define WM8951_DAI 0 + +struct wm8951_setup_data { + unsigned short i2c_address; +}; + +extern struct snd_soc_dai wm8951_dai; +extern struct snd_soc_codec_device soc_codec_dev_wm8951; + +#endif diff --git a/sound/soc/codecs/wm8956.c b/sound/soc/codecs/wm8956.c new file mode 100644 index 0000000..2cc4021 --- /dev/null +++ b/sound/soc/codecs/wm8956.c @@ -0,0 +1,689 @@ +/* + * wm8956.c -- WM8956 ALSA SoC Audio driver + * + * Author: Liam Girdwood + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "wm8956.h" + +#define AUDIO_NAME "wm8956" +#define WM8956_VERSION "0.2" + +struct snd_soc_codec_device soc_codec_dev_wm8956; + +/* + * wm8956 register cache + * We can't read the WM8956 register space when we are + * using 2 wire for device control, so we cache them instead. + */ +static const u16 wm8956_reg[WM8956_CACHEREGNUM] = { + 0x0097, 0x0097, 0x0000, 0x0000, + 0x0000, 0x0008, 0x0000, 0x000a, + 0x01c0, 0x0000, 0x00ff, 0x00ff, + 0x0000, 0x0000, 0x0000, 0x0000, //r15 + 0x0000, 0x007b, 0x0100, 0x0032, + 0x0000, 0x00c3, 0x00c3, 0x01c0, + 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, //r31 + 0x0100, 0x0100, 0x0050, 0x0050, + 0x0050, 0x0050, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0040, 0x0000, + 0x0000, 0x0050, 0x0050, 0x0000, //47 + 0x0002, 0x0037, 0x004d, 0x0080, + 0x0008, 0x0031, 0x0026, 0x00e9, +}; + +/* + * read wm8956 register cache + */ +static inline unsigned int wm8956_read_reg_cache(struct snd_soc_codec *codec, + unsigned int reg) +{ + u16 *cache = codec->reg_cache; + if (reg == WM8956_RESET) + return 0; + if (reg >= WM8956_CACHEREGNUM) + return -1; + return cache[reg]; +} + +/* + * write wm8956 register cache + */ +static inline void wm8956_write_reg_cache(struct snd_soc_codec *codec, + u16 reg, unsigned int value) +{ + u16 *cache = codec->reg_cache; + if (reg >= WM8956_CACHEREGNUM) + return; + cache[reg] = value; +} + +/* + * write to the WM8956 register space + */ +static int wm8956_write(struct snd_soc_codec *codec, unsigned int reg, + unsigned int value) +{ + u8 data[2]; + + /* data is + * D15..D9 WM8956 register offset + * D8...D0 register data + */ + data[0] = (reg << 1) | ((value >> 8) & 0x0001); + data[1] = value & 0x00ff; + + wm8956_write_reg_cache (codec, reg, value); + if (codec->hw_write(codec->control_data, data, 2) == 2) + return 0; + else + return -EIO; +} + +#define wm8956_reset(c) wm8956_write(c, WM8956_RESET, 0) + +/* todo - complete enumerated controls */ +static const char *wm8956_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"}; + +static const struct soc_enum wm8956_enum[] = { + SOC_ENUM_SINGLE(WM8956_DACCTL1, 1, 4, wm8956_deemph), +}; + +/* to complete */ +static const struct snd_kcontrol_new wm8956_snd_controls[] = { + +SOC_DOUBLE_R("Headphone Playback Volume", WM8956_LOUT1, WM8956_ROUT1, + 0, 127, 0), +SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8956_LOUT1, WM8956_ROUT1, + 7, 1, 0), +SOC_DOUBLE_R("PCM Volume", WM8956_LDAC, WM8956_RDAC, + 0, 127, 0), + +SOC_ENUM("Playback De-emphasis", wm8956_enum[0]), +}; + +/* add non dapm controls */ +static int wm8956_add_controls(struct snd_soc_codec *codec) +{ + int err, i; + + for (i = 0; i < ARRAY_SIZE(wm8956_snd_controls); i++) { + if ((err = snd_ctl_add(codec->card, + snd_soc_cnew(&wm8956_snd_controls[i],codec, NULL))) < 0) + return err; + } + + return 0; +} + +/* Left Output Mixer */ +static const struct snd_kcontrol_new wm8956_loutput_mixer_controls[] = { +SOC_DAPM_SINGLE("Left PCM Playback Switch", WM8956_LOUTMIX1, 8, 1, 0), +}; + +/* Right Output Mixer */ +static const struct snd_kcontrol_new wm8956_routput_mixer_controls[] = { +SOC_DAPM_SINGLE("Right PCM Playback Switch", WM8956_ROUTMIX2, 8, 1, 0), +}; + +static const struct snd_soc_dapm_widget wm8956_dapm_widgets[] = { +SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0, + &wm8956_loutput_mixer_controls[0], + ARRAY_SIZE(wm8956_loutput_mixer_controls)), +SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0, + &wm8956_loutput_mixer_controls[0], + ARRAY_SIZE(wm8956_routput_mixer_controls)), +}; + +static int wm8956_add_widgets(struct snd_soc_codec *codec) +{ + snd_soc_dapm_new_controls(codec, wm8956_dapm_widgets, + ARRAY_SIZE(wm8956_dapm_widgets)); + + snd_soc_dapm_new_widgets(codec); + return 0; +} + +static int wm8956_set_dai_fmt(struct snd_soc_dai *codec_dai, + unsigned int fmt) +{ + struct snd_soc_codec *codec = codec_dai->codec; + u16 iface = 0; + + /* set master/slave audio interface */ + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + iface |= 0x0040; + break; + case SND_SOC_DAIFMT_CBS_CFS: + break; + default: + return -EINVAL; + } + + /* interface format */ + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + iface |= 0x0002; + break; + case SND_SOC_DAIFMT_RIGHT_J: + break; + case SND_SOC_DAIFMT_LEFT_J: + iface |= 0x0001; + break; + case SND_SOC_DAIFMT_DSP_A: + iface |= 0x0003; + break; + case SND_SOC_DAIFMT_DSP_B: + iface |= 0x0013; + break; + default: + return -EINVAL; + } + + /* clock inversion */ + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + case SND_SOC_DAIFMT_IB_IF: + iface |= 0x0090; + break; + case SND_SOC_DAIFMT_IB_NF: + iface |= 0x0080; + break; + case SND_SOC_DAIFMT_NB_IF: + iface |= 0x0010; + break; + default: + return -EINVAL; + } + + /* set iface */ + wm8956_write(codec, WM8956_IFACE1, iface); + return 0; +} + +static int wm8956_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->codec; + + u16 iface = wm8956_read_reg_cache(codec, WM8956_IFACE1) & 0xfff3; + + /* bit size */ + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + break; + case SNDRV_PCM_FORMAT_S20_3LE: + iface |= 0x0004; + break; + case SNDRV_PCM_FORMAT_S24_LE: + iface |= 0x0008; + break; + } + + /* set iface */ + wm8956_write(codec, WM8956_IFACE1, iface); + return 0; +} + +static int wm8956_mute(struct snd_soc_dai *dai, int mute) +{ + struct snd_soc_codec *codec = dai->codec; + u16 mute_reg = wm8956_read_reg_cache(codec, WM8956_DACCTL1) & 0xfff7; + + if (mute) + wm8956_write(codec, WM8956_DACCTL1, mute_reg | 0x8); + else + wm8956_write(codec, WM8956_DACCTL1, mute_reg); + return 0; +} + +static int wm8956_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level event) +{ +#if 0 + switch (event) { + case SND_SOC_BIAS_ON: + case SND_SOC_BIAS_PREPARE: + case SND_SOC_BIAS_STANDBY: + case SND_SOC_BIAS_OFF: + break; + } +#endif + // tmp + wm8956_write(codec, WM8956_POWER1, 0xfffe); + wm8956_write(codec, WM8956_POWER2, 0xffff); + wm8956_write(codec, WM8956_POWER3, 0xffff); + codec->bias_level = event; + return 0; +} + +/* PLL divisors */ +struct _pll_div { + u32 pre_div:1; + u32 n:4; + u32 k:24; +}; + +static struct _pll_div pll_div; + +/* The size in bits of the pll divide multiplied by 10 + * to allow rounding later */ +#define FIXED_PLL_SIZE ((1 << 24) * 10) + +static void pll_factors(unsigned int target, unsigned int source) +{ + unsigned long long Kpart; + unsigned int K, Ndiv, Nmod; + + Ndiv = target / source; + if (Ndiv < 6) { + source >>= 1; + pll_div.pre_div = 1; + Ndiv = target / source; + } else + pll_div.pre_div = 0; + + if ((Ndiv < 6) || (Ndiv > 12)) + printk(KERN_WARNING + "WM8956 N value outwith recommended range! N = %d\n",Ndiv); + + pll_div.n = Ndiv; + Nmod = target % source; + Kpart = FIXED_PLL_SIZE * (long long)Nmod; + + do_div(Kpart, source); + + K = Kpart & 0xFFFFFFFF; + + /* Check if we need to round */ + if ((K % 10) >= 5) + K += 5; + + /* Move down to proper range now rounding is done */ + K /= 10; + + pll_div.k = K; +} + +static int wm8956_set_dai_pll(struct snd_soc_dai *codec_dai, + int pll_id, unsigned int freq_in, unsigned int freq_out) +{ + struct snd_soc_codec *codec = codec_dai->codec; + u16 reg; + int found = 0; +#if 0 + if (freq_in == 0 || freq_out == 0) { + /* disable the pll */ + /* turn PLL power off */ + } +#endif + + pll_factors(freq_out * 8, freq_in); + + if (!found) + return -EINVAL; + + reg = wm8956_read_reg_cache(codec, WM8956_PLLN) & 0x1e0; + wm8956_write(codec, WM8956_PLLN, reg | (1<<5) | (pll_div.pre_div << 4) + | pll_div.n); + wm8956_write(codec, WM8956_PLLK1, pll_div.k >> 16 ); + wm8956_write(codec, WM8956_PLLK2, (pll_div.k >> 8) & 0xff); + wm8956_write(codec, WM8956_PLLK3, pll_div.k &0xff); + wm8956_write(codec, WM8956_CLOCK1, 4); + + return 0; +} + +static int wm8956_set_dai_clkdiv(struct snd_soc_dai *codec_dai, + int div_id, int div) +{ + struct snd_soc_codec *codec = codec_dai->codec; + u16 reg; + + switch (div_id) { + case WM8956_SYSCLKSEL: + reg = wm8956_read_reg_cache(codec, WM8956_CLOCK1) & 0x1fe; + wm8956_write(codec, WM8956_CLOCK1, reg | div); + break; + case WM8956_SYSCLKDIV: + reg = wm8956_read_reg_cache(codec, WM8956_CLOCK1) & 0x1f9; + wm8956_write(codec, WM8956_CLOCK1, reg | div); + break; + case WM8956_DACDIV: + reg = wm8956_read_reg_cache(codec, WM8956_CLOCK1) & 0x1c7; + wm8956_write(codec, WM8956_CLOCK1, reg | div); + break; + case WM8956_OPCLKDIV: + reg = wm8956_read_reg_cache(codec, WM8956_PLLN) & 0x03f; + wm8956_write(codec, WM8956_PLLN, reg | div); + break; + case WM8956_DCLKDIV: + reg = wm8956_read_reg_cache(codec, WM8956_CLOCK2) & 0x03f; + wm8956_write(codec, WM8956_CLOCK2, reg | div); + break; + case WM8956_TOCLKSEL: + reg = wm8956_read_reg_cache(codec, WM8956_ADDCTL1) & 0x1fd; + wm8956_write(codec, WM8956_ADDCTL1, reg | div); + break; + default: + return -EINVAL; + } + + return 0; +} + +#define WM8956_RATES \ + (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \ + SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ + SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000) + +#define WM8956_FORMATS \ + (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ + SNDRV_PCM_FMTBIT_S24_LE) + +struct snd_soc_dai wm8956_dai = { + .name = "WM8956", + .playback = { + .stream_name = "Playback", + .channels_min = 1, + .channels_max = 2, + .rates = WM8956_RATES, + .formats = WM8956_FORMATS,}, + .capture = { + .stream_name = "Capture", + .channels_min = 1, + .channels_max = 2, + .rates = WM8956_RATES, + .formats = WM8956_FORMATS,}, + .ops = { + .hw_params = wm8956_hw_params, + .digital_mute = wm8956_mute, + .set_fmt = wm8956_set_dai_fmt, + .set_clkdiv = wm8956_set_dai_clkdiv, + .set_pll = wm8956_set_dai_pll, + }, +}; +EXPORT_SYMBOL_GPL(wm8956_dai); + + +/* To complete PM */ +static int wm8956_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + + wm8956_set_bias_level(codec, SND_SOC_BIAS_OFF); + return 0; +} + +static int wm8956_resume(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + int i; + u8 data[2]; + u16 *cache = codec->reg_cache; + + /* Sync reg_cache with the hardware */ + for (i = 0; i < ARRAY_SIZE(wm8956_reg); i++) { + data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001); + data[1] = cache[i] & 0x00ff; + codec->hw_write(codec->control_data, data, 2); + } + wm8956_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + wm8956_set_bias_level(codec, codec->suspend_bias_level); + return 0; +} + +/* + * initialise the WM8956 driver + * register the mixer and dsp interfaces with the kernel + */ +static int wm8956_init(struct snd_soc_device *socdev) +{ + struct snd_soc_codec *codec = socdev->codec; + int reg, ret = 0; + + codec->name = "WM8956"; + codec->owner = THIS_MODULE; + codec->read = wm8956_read_reg_cache; + codec->write = wm8956_write; + codec->set_bias_level = wm8956_set_bias_level; + codec->dai = &wm8956_dai; + codec->num_dai = 1; + codec->reg_cache_size = ARRAY_SIZE(wm8956_reg); + codec->reg_cache = kmemdup(wm8956_reg, sizeof(wm8956_reg), GFP_KERNEL); + + if (codec->reg_cache == NULL) + return -ENOMEM; + + wm8956_reset(codec); + + /* register pcms */ + ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); + if (ret < 0) { + printk(KERN_ERR "wm8956: failed to create pcms\n"); + goto pcm_err; + } + + /* power on device */ + wm8956_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + + /* set the update bits */ + reg = wm8956_read_reg_cache(codec, WM8956_LOUT1); + wm8956_write(codec, WM8956_LOUT1, reg | 0x0100); + reg = wm8956_read_reg_cache(codec, WM8956_ROUT1); + wm8956_write(codec, WM8956_ROUT1, reg | 0x0100); + + wm8956_add_controls(codec); + wm8956_add_widgets(codec); + ret = snd_soc_init_card(socdev); + if (ret < 0) { + printk(KERN_ERR "wm8956: failed to register card\n"); + goto card_err; + } + return ret; + +card_err: + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); +pcm_err: + kfree(codec->reg_cache); + return ret; +} + +static struct snd_soc_device *wm8956_socdev; + +#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE) + +/* + * WM8956 2 wire address is 0x1a + */ +static unsigned short normal_i2c[] = { 0, I2C_CLIENT_END }; + +/* Magic definition of all other variables and things */ +I2C_CLIENT_INSMOD; + +static struct i2c_driver wm8956_i2c_driver; +static struct i2c_client client_template; + +/* If the i2c layer weren't so broken, we could pass this kind of data + around */ + +static int wm8956_codec_probe(struct i2c_adapter *adap, int addr, int kind) +{ + struct snd_soc_device *socdev = wm8956_socdev; + struct wm8956_setup_data *setup = socdev->codec_data; + struct snd_soc_codec *codec = socdev->codec; + struct i2c_client *i2c; + int ret; + + if (addr != setup->i2c_address) + return -ENODEV; + + client_template.adapter = adap; + client_template.addr = addr; + + i2c = kmemdup(&client_template, sizeof(client_template), GFP_KERNEL); + if (i2c == NULL) { + kfree(codec); + return -ENOMEM; + } + i2c_set_clientdata(i2c, codec); + codec->control_data = i2c; + + ret = i2c_attach_client(i2c); + if (ret < 0) { + pr_err("failed to attach codec at addr %x\n", addr); + goto err; + } + + ret = wm8956_init(socdev); + if (ret < 0) { + pr_err("failed to initialise WM8956\n"); + goto err; + } + return ret; + +err: + kfree(codec); + kfree(i2c); + return ret; +} + +static int wm8956_i2c_detach(struct i2c_client *client) +{ + struct snd_soc_codec* codec = i2c_get_clientdata(client); + i2c_detach_client(client); + kfree(codec->reg_cache); + kfree(client); + return 0; +} + +static int wm8956_i2c_attach(struct i2c_adapter *adap) +{ + return i2c_probe(adap, &addr_data, wm8956_codec_probe); +} + +// tmp +#define I2C_DRIVERID_WM8956 0xfefe + +/* corgi i2c codec control layer */ +static struct i2c_driver wm8956_i2c_driver = { + .driver = { + .name = "WM8956 I2C Codec", + .owner = THIS_MODULE, + }, + .id = I2C_DRIVERID_WM8956, + .attach_adapter = wm8956_i2c_attach, + .detach_client = wm8956_i2c_detach, + .command = NULL, +}; + +static struct i2c_client client_template = { + .name = "WM8956", + .driver = &wm8956_i2c_driver, +}; +#endif + +static int wm8956_probe(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct wm8956_setup_data *setup; + struct snd_soc_codec *codec; + int ret = 0; + + pr_info("WM8956 Audio Codec %s", WM8956_VERSION); + + setup = socdev->codec_data; + codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); + if (codec == NULL) + return -ENOMEM; + + socdev->codec = codec; + mutex_init(&codec->mutex); + INIT_LIST_HEAD(&codec->dapm_widgets); + INIT_LIST_HEAD(&codec->dapm_paths); + + wm8956_socdev = socdev; +#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE) + if (setup->i2c_address) { + normal_i2c[0] = setup->i2c_address; + codec->hw_write = (hw_write_t)i2c_master_send; + ret = i2c_add_driver(&wm8956_i2c_driver); + if (ret != 0) + printk(KERN_ERR "can't add i2c driver"); + } +#else + /* Add other interfaces here */ +#endif + return ret; +} + +/* power down chip */ +static int wm8956_remove(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + + if (codec->control_data) + wm8956_set_bias_level(codec, SND_SOC_BIAS_OFF); + + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); +#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE) + i2c_del_driver(&wm8956_i2c_driver); +#endif + kfree(codec); + + return 0; +} + +struct snd_soc_codec_device soc_codec_dev_wm8956 = { + .probe = wm8956_probe, + .remove = wm8956_remove, + .suspend = wm8956_suspend, + .resume = wm8956_resume, +}; + +EXPORT_SYMBOL_GPL(soc_codec_dev_wm8956); + +static int __init wm8956_modinit(void) +{ + return snd_soc_register_dai(&wm8956_dai); +} +module_init(wm8956_modinit); + +static void __exit wm8956_exit(void) +{ + snd_soc_unregister_dai(&wm8956_dai); +} +module_exit(wm8956_exit); + +MODULE_DESCRIPTION("ASoC WM8956 driver"); +MODULE_AUTHOR("Liam Girdwood"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/wm8956.h b/sound/soc/codecs/wm8956.h new file mode 100644 index 0000000..3fc2e30 --- /dev/null +++ b/sound/soc/codecs/wm8956.h @@ -0,0 +1,116 @@ +/* + * wm8956.h -- WM8956 Soc Audio driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _WM8956_H +#define _WM8956_H + +/* WM8956 register space */ + + +#define WM8956_CACHEREGNUM 56 + +#define WM8956_LINVOL 0x0 +#define WM8956_RINVOL 0x1 +#define WM8956_LOUT1 0x2 +#define WM8956_ROUT1 0x3 +#define WM8956_CLOCK1 0x4 +#define WM8956_DACCTL1 0x5 +#define WM8956_DACCTL2 0x6 +#define WM8956_IFACE1 0x7 +#define WM8956_CLOCK2 0x8 +#define WM8956_IFACE2 0x9 +#define WM8956_LDAC 0xa +#define WM8956_RDAC 0xb + +#define WM8956_RESET 0xf +#define WM8956_3D 0x10 + +#define WM8956_ADDCTL1 0x17 +#define WM8956_ADDCTL2 0x18 +#define WM8956_POWER1 0x19 +#define WM8956_POWER2 0x1a +#define WM8956_ADDCTL3 0x1b +#define WM8956_APOP1 0x1c +#define WM8956_APOP2 0x1d + +#define WM8956_LINPATH 0x20 +#define WM8956_RINPATH 0x21 +#define WM8956_LOUTMIX1 0x22 + +#define WM8956_ROUTMIX2 0x25 +#define WM8956_MONOMIX1 0x26 +#define WM8956_MONOMIX2 0x27 +#define WM8956_LOUT2 0x28 +#define WM8956_ROUT2 0x29 +#define WM8956_MONO 0x2a +#define WM8956_INBMIX1 0x2b +#define WM8956_INBMIX2 0x2c +#define WM8956_BYPASS1 0x2d +#define WM8956_BYPASS2 0x2e +#define WM8956_POWER3 0x2f +#define WM8956_ADDCTL4 0x30 +#define WM8956_CLASSD1 0x31 + +#define WM8956_CLASSD3 0x33 +#define WM8956_PLLN 0x34 +#define WM8956_PLLK1 0x35 +#define WM8956_PLLK2 0x36 +#define WM8956_PLLK3 0x37 + + +/* + * WM8956 Clock dividers + */ +#define WM8956_SYSCLKDIV 0 +#define WM8956_DACDIV 1 +#define WM8956_OPCLKDIV 2 +#define WM8956_DCLKDIV 3 +#define WM8956_TOCLKSEL 4 +#define WM8956_SYSCLKSEL 5 + +#define WM8956_SYSCLK_DIV_1 (0 << 1) +#define WM8956_SYSCLK_DIV_2 (2 << 1) + +#define WM8956_SYSCLK_MCLK (0 << 0) +#define WM8956_SYSCLK_PLL (1 << 0) + +#define WM8956_DAC_DIV_1 (0 << 3) +#define WM8956_DAC_DIV_1_5 (1 << 3) +#define WM8956_DAC_DIV_2 (2 << 3) +#define WM8956_DAC_DIV_3 (3 << 3) +#define WM8956_DAC_DIV_4 (4 << 3) +#define WM8956_DAC_DIV_5_5 (5 << 3) +#define WM8956_DAC_DIV_6 (6 << 3) + +#define WM8956_DCLK_DIV_1_5 (0 << 6) +#define WM8956_DCLK_DIV_2 (1 << 6) +#define WM8956_DCLK_DIV_3 (2 << 6) +#define WM8956_DCLK_DIV_4 (3 << 6) +#define WM8956_DCLK_DIV_6 (4 << 6) +#define WM8956_DCLK_DIV_8 (5 << 6) +#define WM8956_DCLK_DIV_12 (6 << 6) +#define WM8956_DCLK_DIV_16 (7 << 6) + +#define WM8956_TOCLK_F19 (0 << 1) +#define WM8956_TOCLK_F21 (1 << 1) + +#define WM8956_OPCLK_DIV_1 (0 << 0) +#define WM8956_OPCLK_DIV_2 (1 << 0) +#define WM8956_OPCLK_DIV_3 (2 << 0) +#define WM8956_OPCLK_DIV_4 (3 << 0) +#define WM8956_OPCLK_DIV_5_5 (4 << 0) +#define WM8956_OPCLK_DIV_6 (5 << 0) + +struct wm8956_setup_data { + unsigned short i2c_address; +}; + +extern struct snd_soc_dai wm8956_dai; +extern struct snd_soc_codec_device soc_codec_dev_wm8956; + +#endif diff --git a/sound/soc/codecs/wm8960.c b/sound/soc/codecs/wm8960.c new file mode 100644 index 0000000..124acc8 --- /dev/null +++ b/sound/soc/codecs/wm8960.c @@ -0,0 +1,786 @@ +/* + * wm8960.c -- WM8960 ALSA SoC Audio driver + * + * Author: Liam Girdwood + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "wm8960.h" + +#define AUDIO_NAME "wm8960" +#define WM8960_VERSION "0.2" + + +struct snd_soc_codec_device soc_codec_dev_wm8960; + +/* + * wm8960 register cache + * We can't read the WM8960 register space when we are + * using 2 wire for device control, so we cache them instead. + */ +static const u16 wm8960_reg[WM8960_CACHEREGNUM] = { + 0x0097, 0x0097, 0x0000, 0x0000, + 0x0000, 0x0008, 0x0000, 0x000a, + 0x01c0, 0x0000, 0x00ff, 0x00ff, + 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x007b, 0x0100, 0x0032, + 0x0000, 0x00c3, 0x00c3, 0x01c0, + 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, + 0x0100, 0x0100, 0x0050, 0x0050, + 0x0050, 0x0050, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0040, 0x0000, + 0x0000, 0x0050, 0x0050, 0x0000, + 0x0002, 0x0037, 0x004d, 0x0080, + 0x0008, 0x0031, 0x0026, 0x00e9, +}; + +/* + * read wm8960 register cache + */ +static inline unsigned int wm8960_read_reg_cache(struct snd_soc_codec *codec, + unsigned int reg) +{ + u16 *cache = codec->reg_cache; + if (reg == WM8960_RESET) + return 0; + if (reg >= WM8960_CACHEREGNUM) + return -1; + return cache[reg]; +} + +/* + * write wm8960 register cache + */ +static inline void wm8960_write_reg_cache(struct snd_soc_codec *codec, + u16 reg, unsigned int value) +{ + u16 *cache = codec->reg_cache; + if (reg >= WM8960_CACHEREGNUM) + return; + cache[reg] = value; +} + +static inline unsigned int wm8960_read(struct snd_soc_codec *codec, + unsigned int reg) +{ + return wm8960_read_reg_cache(codec, reg); +} + +/* + * write to the WM8960 register space + */ +static int wm8960_write(struct snd_soc_codec *codec, unsigned int reg, + unsigned int value) +{ + u8 data[2]; + + /* data is + * D15..D9 WM8960 register offset + * D8...D0 register data + */ + data[0] = (reg << 1) | ((value >> 8) & 0x0001); + data[1] = value & 0x00ff; + + wm8960_write_reg_cache(codec, reg, value); + if (codec->hw_write(codec->control_data, data, 2) == 2) + return 0; + else + return -EIO; +} + +#define wm8960_reset(c) wm8960_write(c, WM8960_RESET, 0) + +/* enumerated controls */ +static const char *wm8960_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"}; +static const char *wm8960_polarity[] = {"No Inversion", "Left Inverted", + "Right Inverted", "Stereo Inversion"}; +static const char *wm8960_3d_upper_cutoff[] = {"High", "Low"}; +static const char *wm8960_3d_lower_cutoff[] = {"Low", "High"}; +static const char *wm8960_alcfunc[] = {"Off", "Right", "Left", "Stereo"}; +static const char *wm8960_alcmode[] = {"ALC", "Limiter"}; + +static const struct soc_enum wm8960_enum[] = { + SOC_ENUM_SINGLE(WM8960_DACCTL1, 1, 4, wm8960_deemph), + SOC_ENUM_SINGLE(WM8960_DACCTL1, 5, 4, wm8960_polarity), + SOC_ENUM_SINGLE(WM8960_DACCTL2, 5, 4, wm8960_polarity), + SOC_ENUM_SINGLE(WM8960_3D, 6, 2, wm8960_3d_upper_cutoff), + SOC_ENUM_SINGLE(WM8960_3D, 5, 2, wm8960_3d_lower_cutoff), + SOC_ENUM_SINGLE(WM8960_ALC1, 7, 4, wm8960_alcfunc), + SOC_ENUM_SINGLE(WM8960_ALC3, 8, 2, wm8960_alcmode), +}; + +/* to complete */ +static const struct snd_kcontrol_new wm8960_snd_controls[] = { +SOC_DOUBLE_R("Capture Volume", WM8960_LINVOL, WM8960_RINVOL, + 0, 63, 0), +SOC_DOUBLE_R("Capture Volume ZC Switch", WM8960_LINVOL, WM8960_RINVOL, + 6, 1, 0), +SOC_DOUBLE_R("Capture Switch", WM8960_LINVOL, WM8960_RINVOL, + 7, 1, 0), +SOC_DOUBLE_R("Headphone Playback Volume", WM8960_LOUT1, WM8960_ROUT1, + 0, 127, 0), +SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8960_LOUT1, WM8960_ROUT1, + 7, 1, 0), +SOC_SINGLE("PCM Playback -6dB Switch", WM8960_DACCTL1, 7, 1, 0), +SOC_ENUM("ADC Polarity", wm8960_enum[1]), +SOC_ENUM("Playback De-emphasis", wm8960_enum[0]), +SOC_SINGLE("ADC High Pass Filter Switch", WM8960_DACCTL1, 0, 1, 0), + +SOC_ENUM("DAC Polarity", wm8960_enum[2]), + +SOC_DOUBLE_R("PCM Volume", WM8960_LDAC, WM8960_RDAC, + 0, 127, 0), + +SOC_ENUM("3D Filter Upper Cut-Off", wm8960_enum[3]), +SOC_ENUM("3D Filter Lower Cut-Off", wm8960_enum[4]), +SOC_SINGLE("3D Volume", WM8960_3D, 1, 15, 0), +SOC_SINGLE("3D Switch", WM8960_3D, 0, 1, 0), + +SOC_ENUM("ALC Function", wm8960_enum[5]), +SOC_SINGLE("ALC Max Gain", WM8960_ALC1, 4, 7, 0), +SOC_SINGLE("ALC Target", WM8960_ALC1, 0, 15, 1), +SOC_SINGLE("ALC Min Gain", WM8960_ALC2, 4, 7, 0), +SOC_SINGLE("ALC Hold Time", WM8960_ALC2, 0, 15, 0), +SOC_ENUM("ALC Mode", wm8960_enum[6]), +SOC_SINGLE("ALC Decay", WM8960_ALC3, 4, 15, 0), +SOC_SINGLE("ALC Attack", WM8960_ALC3, 0, 15, 0), + +SOC_SINGLE("Noise Gate Threshold", WM8960_NOISEG, 3, 31, 0), +SOC_SINGLE("Noise Gate Switch", WM8960_NOISEG, 0, 1, 0), + +SOC_DOUBLE_R("ADC PCM Capture Volume", WM8960_LINPATH, WM8960_RINPATH, + 0, 127, 0), +}; + +/* add non dapm controls */ +static int wm8960_add_controls(struct snd_soc_codec *codec) +{ + int err, i; + + for (i = 0; i < ARRAY_SIZE(wm8960_snd_controls); i++) { + err = snd_ctl_add(codec->card, + snd_soc_cnew(&wm8960_snd_controls[i], + codec, NULL)); + if (err < 0) + return err; + } + + return 0; +} + +/* Left Output Mixer */ +static const struct snd_kcontrol_new wm8960_loutput_mixer_controls[] = { +SOC_DAPM_SINGLE("Left PCM Playback Switch", WM8960_LOUTMIX1, 8, 1, 0), +}; + +/* Right Output Mixer */ +static const struct snd_kcontrol_new wm8960_routput_mixer_controls[] = { +SOC_DAPM_SINGLE("Right PCM Playback Switch", WM8960_ROUTMIX2, 8, 1, 0), +}; + +static const struct snd_soc_dapm_widget wm8960_dapm_widgets[] = { +SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0, + &wm8960_loutput_mixer_controls[0], + ARRAY_SIZE(wm8960_loutput_mixer_controls)), +SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0, + &wm8960_loutput_mixer_controls[0], + ARRAY_SIZE(wm8960_routput_mixer_controls)), +}; + +static int wm8960_add_widgets(struct snd_soc_codec *codec) +{ + snd_soc_dapm_new_controls(codec, wm8960_dapm_widgets, + ARRAY_SIZE(wm8960_dapm_widgets)); + + snd_soc_dapm_new_widgets(codec); + return 0; +} + +static int wm8960_set_dai_fmt(struct snd_soc_dai *codec_dai, + unsigned int fmt) +{ + struct snd_soc_codec *codec = codec_dai->codec; + u16 iface = 0; + + /* set master/slave audio interface */ + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + iface |= 0x0040; + break; + case SND_SOC_DAIFMT_CBS_CFS: + break; + default: + return -EINVAL; + } + + /* interface format */ + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + iface |= 0x0002; + break; + case SND_SOC_DAIFMT_RIGHT_J: + break; + case SND_SOC_DAIFMT_LEFT_J: + iface |= 0x0001; + break; + case SND_SOC_DAIFMT_DSP_A: + iface |= 0x0003; + break; + case SND_SOC_DAIFMT_DSP_B: + iface |= 0x0013; + break; + default: + return -EINVAL; + } + + /* clock inversion */ + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + case SND_SOC_DAIFMT_IB_IF: + iface |= 0x0090; + break; + case SND_SOC_DAIFMT_IB_NF: + iface |= 0x0080; + break; + case SND_SOC_DAIFMT_NB_IF: + iface |= 0x0010; + break; + default: + return -EINVAL; + } + + /* set iface */ + wm8960_write(codec, WM8960_IFACE1, iface); + return 0; +} + +static int wm8960_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->codec; + u16 iface = wm8960_read(codec, WM8960_IFACE1) & 0xfff3; + + /* bit size */ + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + break; + case SNDRV_PCM_FORMAT_S20_3LE: + iface |= 0x0004; + break; + case SNDRV_PCM_FORMAT_S24_LE: + iface |= 0x0008; + break; + } + + /* set iface */ + wm8960_write(codec, WM8960_IFACE1, iface); + return 0; +} + +static int wm8960_mute(struct snd_soc_dai *dai, int mute) +{ + struct snd_soc_codec *codec = dai->codec; + u16 mute_reg = wm8960_read(codec, WM8960_DACCTL1) & 0xfff7; + + if (mute) + wm8960_write(codec, WM8960_DACCTL1, mute_reg | 0x8); + else + wm8960_write(codec, WM8960_DACCTL1, mute_reg); + return 0; +} + +static int wm8960_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level) +{ + u16 power1 = wm8960_read(codec, WM8960_POWER1); + u16 power2 = wm8960_read(codec, WM8960_POWER2); + + switch (level) { + case SND_SOC_BIAS_ON: + power1 &= ~0x180; + power1 |= 0xc0; + break; + + case SND_SOC_BIAS_PREPARE: + break; + + case SND_SOC_BIAS_STANDBY: + power1 &= ~0x180; + power1 |= 0x140; + wm8960_write(codec, WM8960_ADDCTL1, + wm8960_read(codec, WM8960_ADDCTL1) | 1); + break; + + case SND_SOC_BIAS_OFF: + wm8960_write(codec, WM8960_APOP1, 0x94); + wm8960_write(codec, WM8960_POWER1, power1 & ~0x1c0); + mdelay(600); /* Ensure HP output has discharged */ + wm8960_write(codec, WM8960_ADDCTL1, + wm8960_read(codec, WM8960_ADDCTL1) & ~1); + return 0; + } + + wm8960_write(codec, WM8960_POWER1, power1 | 0x03e); + wm8960_write(codec, WM8960_POWER2, power2 | 0x1fe); + wm8960_write(codec, WM8960_POWER3, 0xffff); + codec->bias_level = level; + + return 0; +} + +/* PLL divisors */ +struct _pll_div { + u32 pre_div:1; + u32 n:4; + u32 k:24; +}; + +/* The size in bits of the pll divide multiplied by 10 + * to allow rounding later */ +#define FIXED_PLL_SIZE ((1 << 24) * 10) + +static int pll_factors(unsigned int source, unsigned int target, + struct _pll_div *pll_div) +{ + unsigned long long Kpart; + unsigned int K, Ndiv, Nmod; + + pr_debug("WM8960 PLL: setting %dHz->%dHz\n", source, target); + + /* Scale up target to PLL operating frequency */ + target *= 4; + + Ndiv = target / source; + if (Ndiv < 6) { + source >>= 1; + pll_div->pre_div = 1; + Ndiv = target / source; + } else + pll_div->pre_div = 0; + + if ((Ndiv < 6) || (Ndiv > 12)) { + pr_err("WM8960 PLL: Unsupported N=%d\n", Ndiv); + return -EINVAL; + } + + pll_div->n = Ndiv; + Nmod = target % source; + Kpart = FIXED_PLL_SIZE * (long long)Nmod; + + do_div(Kpart, source); + + K = Kpart & 0xFFFFFFFF; + + /* Check if we need to round */ + if ((K % 10) >= 5) + K += 5; + + /* Move down to proper range now rounding is done */ + K /= 10; + + pll_div->k = K; + + pr_debug("WM8960 PLL: N=%x K=%x pre_div=%d\n", + pll_div->n, pll_div->k, pll_div->pre_div); + + return 0; +} + +static int wm8960_set_dai_pll(struct snd_soc_dai *codec_dai, + int pll_id, unsigned int freq_in, unsigned int freq_out) +{ + struct snd_soc_codec *codec = codec_dai->codec; + u16 reg; + static struct _pll_div pll_div; + int ret; + + if (freq_out) { + ret = pll_factors(freq_in, freq_out, &pll_div); + if (ret != 0) + return ret; + } + + /* Disable the PLL: even if we are changing the frequency the + * PLL needs to be disabled while we do so. */ + wm8960_write(codec, WM8960_CLOCK1, + wm8960_read(codec, WM8960_CLOCK1) & ~1); + wm8960_write(codec, WM8960_POWER2, + wm8960_read(codec, WM8960_POWER2) & ~1); + + reg = wm8960_read(codec, WM8960_PLL1) & ~0x3f; + reg |= pll_div.pre_div << 4; + reg |= pll_div.n; + + if (pll_div.k) { + reg |= 0x20; + + wm8960_write(codec, WM8960_PLL2, (pll_div.k >> 16) & 0x7f); + wm8960_write(codec, WM8960_PLL3, (pll_div.k >> 8) & 0xff); + wm8960_write(codec, WM8960_PLL4, pll_div.k & 0xff); + } + wm8960_write(codec, WM8960_PLL1, reg); + + /* Turn it on */ + wm8960_write(codec, WM8960_POWER2, + wm8960_read(codec, WM8960_POWER2) | 1); + msleep(250); + wm8960_write(codec, WM8960_CLOCK1, + wm8960_read(codec, WM8960_CLOCK1) | 1); + + return 0; +} + +static int wm8960_set_dai_clkdiv(struct snd_soc_dai *codec_dai, + int div_id, int div) +{ + struct snd_soc_codec *codec = codec_dai->codec; + u16 reg; + + switch (div_id) { + case WM8960_SYSCLKSEL: + reg = wm8960_read(codec, WM8960_CLOCK1) & 0x1fe; + wm8960_write(codec, WM8960_CLOCK1, reg | div); + break; + case WM8960_SYSCLKDIV: + reg = wm8960_read(codec, WM8960_CLOCK1) & 0x1f9; + wm8960_write(codec, WM8960_CLOCK1, reg | div); + break; + case WM8960_DACDIV: + reg = wm8960_read(codec, WM8960_CLOCK1) & 0x1c7; + wm8960_write(codec, WM8960_CLOCK1, reg | div); + break; + case WM8960_OPCLKDIV: + reg = wm8960_read(codec, WM8960_PLL1) & 0x03f; + wm8960_write(codec, WM8960_PLL1, reg | div); + break; + case WM8960_DCLKDIV: + reg = wm8960_read(codec, WM8960_CLOCK2) & 0x03f; + wm8960_write(codec, WM8960_CLOCK2, reg | div); + break; + case WM8960_TOCLKSEL: + reg = wm8960_read(codec, WM8960_ADDCTL1) & 0x1fd; + wm8960_write(codec, WM8960_ADDCTL1, reg | div); + break; + default: + return -EINVAL; + } + + return 0; +} + +#define WM8960_RATES SNDRV_PCM_RATE_8000_48000 + +#define WM8960_FORMATS \ + (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ + SNDRV_PCM_FMTBIT_S24_LE) + +struct snd_soc_dai wm8960_dai = { + .name = "WM8960", + .playback = { + .stream_name = "Playback", + .channels_min = 1, + .channels_max = 2, + .rates = WM8960_RATES, + .formats = WM8960_FORMATS,}, + .capture = { + .stream_name = "Capture", + .channels_min = 1, + .channels_max = 2, + .rates = WM8960_RATES, + .formats = WM8960_FORMATS,}, + .ops = { + .hw_params = wm8960_hw_params, + .digital_mute = wm8960_mute, + .set_fmt = wm8960_set_dai_fmt, + .set_clkdiv = wm8960_set_dai_clkdiv, + .set_pll = wm8960_set_dai_pll, + }, +}; +EXPORT_SYMBOL_GPL(wm8960_dai); + + +/* To complete PM */ +static int wm8960_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + + wm8960_set_bias_level(codec, SND_SOC_BIAS_OFF); + return 0; +} + +static int wm8960_resume(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + int i; + u8 data[2]; + u16 *cache = codec->reg_cache; + + /* Sync reg_cache with the hardware */ + for (i = 0; i < ARRAY_SIZE(wm8960_reg); i++) { + data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001); + data[1] = cache[i] & 0x00ff; + codec->hw_write(codec->control_data, data, 2); + } + + wm8960_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + wm8960_set_bias_level(codec, codec->suspend_bias_level); + return 0; +} + +/* + * initialise the WM8960 driver + * register the mixer and dsp interfaces with the kernel + */ +static int wm8960_init(struct snd_soc_device *socdev) +{ + struct snd_soc_codec *codec = socdev->codec; + int reg, ret = 0; + + codec->name = "WM8960"; + codec->owner = THIS_MODULE; + codec->read = wm8960_read; + codec->write = wm8960_write; + codec->set_bias_level = wm8960_set_bias_level; + codec->dai = &wm8960_dai; + codec->num_dai = 1; + codec->reg_cache_size = ARRAY_SIZE(wm8960_reg); + codec->reg_cache = kmemdup(wm8960_reg, sizeof(wm8960_reg), GFP_KERNEL); + + if (codec->reg_cache == NULL) + return -ENOMEM; + + wm8960_reset(codec); + + /* register pcms */ + ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); + if (ret < 0) { + printk(KERN_ERR "wm8960: failed to create pcms\n"); + goto pcm_err; + } + + /* Initial power on sequence */ + wm8960_write(codec, WM8960_APOP1, 0x94); + wm8960_write(codec, WM8960_APOP2, 0x40); + msleep(400); /* HP output discharge */ + wm8960_write(codec, WM8960_POWER2, 0x60); + wm8960_write(codec, WM8960_APOP2, 0); + wm8960_write(codec, WM8960_POWER1, 0x80); + msleep(400); /* VMID initial charge */ + wm8960_write(codec, WM8960_POWER1, 0x140); + wm8960_write(codec, WM8960_APOP1, 0); + + wm8960_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + + /* set the update bits */ + reg = wm8960_read(codec, WM8960_LOUT1); + wm8960_write(codec, WM8960_LOUT1, reg | 0x0100); + reg = wm8960_read(codec, WM8960_ROUT1); + wm8960_write(codec, WM8960_ROUT1, reg | 0x0100); + + wm8960_add_controls(codec); + wm8960_add_widgets(codec); + ret = snd_soc_init_card(socdev); + if (ret < 0) { + printk(KERN_ERR "wm8960: failed to register card\n"); + goto card_err; + } + return ret; + +card_err: + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); +pcm_err: + kfree(codec->reg_cache); + return ret; +} + +static struct snd_soc_device *wm8960_socdev; + +#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) + +/* + * WM8960 2 wire address is 0x1a + */ +static unsigned short normal_i2c[] = { 0, I2C_CLIENT_END }; + +/* Magic definition of all other variables and things */ +I2C_CLIENT_INSMOD; + +static struct i2c_driver wm8960_i2c_driver; +static struct i2c_client client_template; + +/* If the i2c layer weren't so broken, we could pass this kind of data + around */ + +static int wm8960_codec_probe(struct i2c_adapter *adap, int addr, int kind) +{ + struct snd_soc_device *socdev = wm8960_socdev; + struct wm8960_setup_data *setup = socdev->codec_data; + struct snd_soc_codec *codec = socdev->codec; + struct i2c_client *i2c; + int ret; + + if (addr != setup->i2c_address) + return -ENODEV; + + client_template.adapter = adap; + client_template.addr = addr; + + i2c = kmemdup(&client_template, sizeof(client_template), GFP_KERNEL); + if (i2c == NULL) { + kfree(codec); + return -ENOMEM; + } + i2c_set_clientdata(i2c, codec); + codec->control_data = i2c; + + ret = i2c_attach_client(i2c); + if (ret < 0) { + pr_err("failed to attach codec at addr %x\n", addr); + goto err; + } + + ret = wm8960_init(socdev); + if (ret < 0) { + pr_err("failed to initialise WM8960\n"); + goto err; + } + return ret; + +err: + kfree(codec); + kfree(i2c); + return ret; +} + +static int wm8960_i2c_detach(struct i2c_client *client) +{ + struct snd_soc_codec *codec = i2c_get_clientdata(client); + i2c_detach_client(client); + kfree(codec->reg_cache); + kfree(client); + return 0; +} + +static int wm8960_i2c_attach(struct i2c_adapter *adap) +{ + return i2c_probe(adap, &addr_data, wm8960_codec_probe); +} + +/* corgi i2c codec control layer */ +static struct i2c_driver wm8960_i2c_driver = { + .driver = { + .name = "WM8960 I2C Codec", + .owner = THIS_MODULE, + }, + .attach_adapter = wm8960_i2c_attach, + .detach_client = wm8960_i2c_detach, + .command = NULL, +}; + +static struct i2c_client client_template = { + .name = "WM8960", + .driver = &wm8960_i2c_driver, +}; +#endif + +static int wm8960_probe(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct wm8960_setup_data *setup; + struct snd_soc_codec *codec; + int ret = 0; + + pr_info("WM8960 Audio Codec %s", WM8960_VERSION); + + setup = socdev->codec_data; + codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); + if (codec == NULL) + return -ENOMEM; + + socdev->codec = codec; + mutex_init(&codec->mutex); + INIT_LIST_HEAD(&codec->dapm_widgets); + INIT_LIST_HEAD(&codec->dapm_paths); + + wm8960_socdev = socdev; +#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) + if (setup->i2c_address) { + normal_i2c[0] = setup->i2c_address; + codec->hw_write = (hw_write_t)i2c_master_send; + ret = i2c_add_driver(&wm8960_i2c_driver); + if (ret != 0) + printk(KERN_ERR "can't add i2c driver"); + } +#else + /* Add other interfaces here */ +#endif + return ret; +} + +/* power down chip */ +static int wm8960_remove(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + + if (codec->control_data) + wm8960_set_bias_level(codec, SND_SOC_BIAS_OFF); + + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); +#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) + i2c_del_driver(&wm8960_i2c_driver); +#endif + kfree(codec); + + return 0; +} + +struct snd_soc_codec_device soc_codec_dev_wm8960 = { + .probe = wm8960_probe, + .remove = wm8960_remove, + .suspend = wm8960_suspend, + .resume = wm8960_resume, +}; +EXPORT_SYMBOL_GPL(soc_codec_dev_wm8960); + +static int __init wm8960_modinit(void) +{ + return snd_soc_register_dai(&wm8960_dai); +} +module_init(wm8960_modinit); + +static void __exit wm8960_exit(void) +{ + snd_soc_unregister_dai(&wm8960_dai); +} +module_exit(wm8960_exit); + +MODULE_DESCRIPTION("ASoC WM8960 driver"); +MODULE_AUTHOR("Liam Girdwood"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/wm8960.h b/sound/soc/codecs/wm8960.h new file mode 100644 index 0000000..8132d06 --- /dev/null +++ b/sound/soc/codecs/wm8960.h @@ -0,0 +1,121 @@ +/* + * wm8960.h -- WM8960 Soc Audio driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _WM8960_H +#define _WM8960_H + +/* WM8960 register space */ + + +#define WM8960_CACHEREGNUM 56 + +#define WM8960_LINVOL 0x0 +#define WM8960_RINVOL 0x1 +#define WM8960_LOUT1 0x2 +#define WM8960_ROUT1 0x3 +#define WM8960_CLOCK1 0x4 +#define WM8960_DACCTL1 0x5 +#define WM8960_DACCTL2 0x6 +#define WM8960_IFACE1 0x7 +#define WM8960_CLOCK2 0x8 +#define WM8960_IFACE2 0x9 +#define WM8960_LDAC 0xa +#define WM8960_RDAC 0xb + +#define WM8960_RESET 0xf +#define WM8960_3D 0x10 +#define WM8960_ALC1 0x11 +#define WM8960_ALC2 0x12 +#define WM8960_ALC3 0x13 +#define WM8960_NOISEG 0x14 +#define WM8960_LADC 0x15 +#define WM8960_RADC 0x16 +#define WM8960_ADDCTL1 0x17 +#define WM8960_ADDCTL2 0x18 +#define WM8960_POWER1 0x19 +#define WM8960_POWER2 0x1a +#define WM8960_ADDCTL3 0x1b +#define WM8960_APOP1 0x1c +#define WM8960_APOP2 0x1d + +#define WM8960_LINPATH 0x20 +#define WM8960_RINPATH 0x21 +#define WM8960_LOUTMIX1 0x22 + +#define WM8960_ROUTMIX2 0x25 +#define WM8960_MONOMIX1 0x26 +#define WM8960_MONOMIX2 0x27 +#define WM8960_LOUT2 0x28 +#define WM8960_ROUT2 0x29 +#define WM8960_MONO 0x2a +#define WM8960_INBMIX1 0x2b +#define WM8960_INBMIX2 0x2c +#define WM8960_BYPASS1 0x2d +#define WM8960_BYPASS2 0x2e +#define WM8960_POWER3 0x2f +#define WM8960_ADDCTL4 0x30 +#define WM8960_CLASSD1 0x31 + +#define WM8960_CLASSD3 0x33 +#define WM8960_PLL1 0x34 +#define WM8960_PLL2 0x35 +#define WM8960_PLL3 0x36 +#define WM8960_PLL4 0x37 + + +/* + * WM8960 Clock dividers + */ +#define WM8960_SYSCLKDIV 0 +#define WM8960_DACDIV 1 +#define WM8960_OPCLKDIV 2 +#define WM8960_DCLKDIV 3 +#define WM8960_TOCLKSEL 4 +#define WM8960_SYSCLKSEL 5 + +#define WM8960_SYSCLK_DIV_1 (0 << 1) +#define WM8960_SYSCLK_DIV_2 (2 << 1) + +#define WM8960_SYSCLK_MCLK (0 << 0) +#define WM8960_SYSCLK_PLL (1 << 0) + +#define WM8960_DAC_DIV_1 (0 << 3) +#define WM8960_DAC_DIV_1_5 (1 << 3) +#define WM8960_DAC_DIV_2 (2 << 3) +#define WM8960_DAC_DIV_3 (3 << 3) +#define WM8960_DAC_DIV_4 (4 << 3) +#define WM8960_DAC_DIV_5_5 (5 << 3) +#define WM8960_DAC_DIV_6 (6 << 3) + +#define WM8960_DCLK_DIV_1_5 (0 << 6) +#define WM8960_DCLK_DIV_2 (1 << 6) +#define WM8960_DCLK_DIV_3 (2 << 6) +#define WM8960_DCLK_DIV_4 (3 << 6) +#define WM8960_DCLK_DIV_6 (4 << 6) +#define WM8960_DCLK_DIV_8 (5 << 6) +#define WM8960_DCLK_DIV_12 (6 << 6) +#define WM8960_DCLK_DIV_16 (7 << 6) + +#define WM8960_TOCLK_F19 (0 << 1) +#define WM8960_TOCLK_F21 (1 << 1) + +#define WM8960_OPCLK_DIV_1 (0 << 0) +#define WM8960_OPCLK_DIV_2 (1 << 0) +#define WM8960_OPCLK_DIV_3 (2 << 0) +#define WM8960_OPCLK_DIV_4 (3 << 0) +#define WM8960_OPCLK_DIV_5_5 (4 << 0) +#define WM8960_OPCLK_DIV_6 (5 << 0) + +struct wm8960_setup_data { + unsigned short i2c_address; +}; + +extern struct snd_soc_dai wm8960_dai; +extern struct snd_soc_codec_device soc_codec_dev_wm8960; + +#endif diff --git a/sound/soc/codecs/wm8971.c b/sound/soc/codecs/wm8971.c index 88ead7f..c8bd9b0 100644 --- a/sound/soc/codecs/wm8971.c +++ b/sound/soc/codecs/wm8971.c @@ -195,21 +195,6 @@ static const struct snd_kcontrol_new wm8971_snd_controls[] = { SOC_DOUBLE_R("Mic Boost", WM8971_LADCIN, WM8971_RADCIN, 4, 3, 0), }; -/* add non-DAPM controls */ -static int wm8971_add_controls(struct snd_soc_codec *codec) -{ - int err, i; - - for (i = 0; i < ARRAY_SIZE(wm8971_snd_controls); i++) { - err = snd_ctl_add(codec->card, - snd_soc_cnew(&wm8971_snd_controls[i], - codec, NULL)); - if (err < 0) - return err; - } - return 0; -} - /* * DAPM Controls */ @@ -745,7 +730,8 @@ static int wm8971_init(struct snd_soc_device *socdev) reg = wm8971_read_reg_cache(codec, WM8971_RINVOL); wm8971_write(codec, WM8971_RINVOL, reg | 0x0100); - wm8971_add_controls(codec); + snd_soc_add_controls(codec, wm8971_snd_controls, + ARRAY_SIZE(wm8971_snd_controls)); wm8971_add_widgets(codec); ret = snd_soc_init_card(socdev); if (ret < 0) { diff --git a/sound/soc/codecs/wm8974.c b/sound/soc/codecs/wm8974.c new file mode 100644 index 0000000..7baf6ff --- /dev/null +++ b/sound/soc/codecs/wm8974.c @@ -0,0 +1,844 @@ +/* + * wm8974.c -- WM8974 ALSA Soc Audio driver + * + * Copyright 2006 Wolfson Microelectronics PLC. + * + * Author: Liam Girdwood + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "wm8974.h" + +#define AUDIO_NAME "wm8974" +#define WM8974_VERSION "0.6" + +struct snd_soc_codec_device soc_codec_dev_wm8974; + +/* + * wm8974 register cache + * We can't read the WM8974 register space when we are + * using 2 wire for device control, so we cache them instead. + */ +static const u16 wm8974_reg[WM8974_CACHEREGNUM] = { + 0x0000, 0x0000, 0x0000, 0x0000, + 0x0050, 0x0000, 0x0140, 0x0000, + 0x0000, 0x0000, 0x0000, 0x00ff, + 0x0000, 0x0000, 0x0100, 0x00ff, + 0x0000, 0x0000, 0x012c, 0x002c, + 0x002c, 0x002c, 0x002c, 0x0000, + 0x0032, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, + 0x0038, 0x000b, 0x0032, 0x0000, + 0x0008, 0x000c, 0x0093, 0x00e9, + 0x0000, 0x0000, 0x0000, 0x0000, + 0x0003, 0x0010, 0x0000, 0x0000, + 0x0000, 0x0002, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0039, 0x0000, + 0x0000, +}; + +/* + * read wm8974 register cache + */ +static inline unsigned int wm8974_read_reg_cache(struct snd_soc_codec * codec, + unsigned int reg) +{ + u16 *cache = codec->reg_cache; + if (reg == WM8974_RESET) + return 0; + if (reg >= WM8974_CACHEREGNUM) + return -1; + return cache[reg]; +} + +/* + * write wm8974 register cache + */ +static inline void wm8974_write_reg_cache(struct snd_soc_codec *codec, + u16 reg, unsigned int value) +{ + u16 *cache = codec->reg_cache; + if (reg >= WM8974_CACHEREGNUM) + return; + cache[reg] = value; +} + +/* + * write to the WM8974 register space + */ +static int wm8974_write(struct snd_soc_codec *codec, unsigned int reg, + unsigned int value) +{ + u8 data[2]; + + /* data is + * D15..D9 WM8974 register offset + * D8...D0 register data + */ + data[0] = (reg << 1) | ((value >> 8) & 0x0001); + data[1] = value & 0x00ff; + + wm8974_write_reg_cache (codec, reg, value); + if (codec->hw_write(codec->control_data, data, 2) == 2) + return 0; + else + return -EIO; +} + +#define wm8974_reset(c) wm8974_write(c, WM8974_RESET, 0) + +static const char *wm8974_companding[] = {"Off", "NC", "u-law", "A-law" }; +static const char *wm8974_deemp[] = {"None", "32kHz", "44.1kHz", "48kHz" }; +static const char *wm8974_eqmode[] = {"Capture", "Playback" }; +static const char *wm8974_bw[] = {"Narrow", "Wide" }; +static const char *wm8974_eq1[] = {"80Hz", "105Hz", "135Hz", "175Hz" }; +static const char *wm8974_eq2[] = {"230Hz", "300Hz", "385Hz", "500Hz" }; +static const char *wm8974_eq3[] = {"650Hz", "850Hz", "1.1kHz", "1.4kHz" }; +static const char *wm8974_eq4[] = {"1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz" }; +static const char *wm8974_eq5[] = {"5.3kHz", "6.9kHz", "9kHz", "11.7kHz" }; +static const char *wm8974_alc[] = {"ALC", "Limiter" }; + +static const struct soc_enum wm8974_enum[] = { + SOC_ENUM_SINGLE(WM8974_COMP, 1, 4, wm8974_companding), /* adc */ + SOC_ENUM_SINGLE(WM8974_COMP, 3, 4, wm8974_companding), /* dac */ + SOC_ENUM_SINGLE(WM8974_DAC, 4, 4, wm8974_deemp), + SOC_ENUM_SINGLE(WM8974_EQ1, 8, 2, wm8974_eqmode), + + SOC_ENUM_SINGLE(WM8974_EQ1, 5, 4, wm8974_eq1), + SOC_ENUM_SINGLE(WM8974_EQ2, 8, 2, wm8974_bw), + SOC_ENUM_SINGLE(WM8974_EQ2, 5, 4, wm8974_eq2), + SOC_ENUM_SINGLE(WM8974_EQ3, 8, 2, wm8974_bw), + + SOC_ENUM_SINGLE(WM8974_EQ3, 5, 4, wm8974_eq3), + SOC_ENUM_SINGLE(WM8974_EQ4, 8, 2, wm8974_bw), + SOC_ENUM_SINGLE(WM8974_EQ4, 5, 4, wm8974_eq4), + SOC_ENUM_SINGLE(WM8974_EQ5, 8, 2, wm8974_bw), + + SOC_ENUM_SINGLE(WM8974_EQ5, 5, 4, wm8974_eq5), + SOC_ENUM_SINGLE(WM8974_ALC3, 8, 2, wm8974_alc), +}; + +static const struct snd_kcontrol_new wm8974_snd_controls[] = { + +SOC_SINGLE("Digital Loopback Switch", WM8974_COMP, 0, 1, 0), + +SOC_ENUM("DAC Companding", wm8974_enum[1]), +SOC_ENUM("ADC Companding", wm8974_enum[0]), + +SOC_ENUM("Playback De-emphasis", wm8974_enum[2]), +SOC_SINGLE("DAC Inversion Switch", WM8974_DAC, 0, 1, 0), + +SOC_SINGLE("PCM Volume", WM8974_DACVOL, 0, 127, 0), + +SOC_SINGLE("High Pass Filter Switch", WM8974_ADC, 8, 1, 0), +SOC_SINGLE("High Pass Cut Off", WM8974_ADC, 4, 7, 0), +SOC_SINGLE("ADC Inversion Switch", WM8974_COMP, 0, 1, 0), + +SOC_SINGLE("Capture Volume", WM8974_ADCVOL, 0, 127, 0), + +SOC_ENUM("Equaliser Function", wm8974_enum[3]), +SOC_ENUM("EQ1 Cut Off", wm8974_enum[4]), +SOC_SINGLE("EQ1 Volume", WM8974_EQ1, 0, 31, 1), + +SOC_ENUM("Equaliser EQ2 Bandwith", wm8974_enum[5]), +SOC_ENUM("EQ2 Cut Off", wm8974_enum[6]), +SOC_SINGLE("EQ2 Volume", WM8974_EQ2, 0, 31, 1), + +SOC_ENUM("Equaliser EQ3 Bandwith", wm8974_enum[7]), +SOC_ENUM("EQ3 Cut Off", wm8974_enum[8]), +SOC_SINGLE("EQ3 Volume", WM8974_EQ3, 0, 31, 1), + +SOC_ENUM("Equaliser EQ4 Bandwith", wm8974_enum[9]), +SOC_ENUM("EQ4 Cut Off", wm8974_enum[10]), +SOC_SINGLE("EQ4 Volume", WM8974_EQ4, 0, 31, 1), + +SOC_ENUM("Equaliser EQ5 Bandwith", wm8974_enum[11]), +SOC_ENUM("EQ5 Cut Off", wm8974_enum[12]), +SOC_SINGLE("EQ5 Volume", WM8974_EQ5, 0, 31, 1), + +SOC_SINGLE("DAC Playback Limiter Switch", WM8974_DACLIM1, 8, 1, 0), +SOC_SINGLE("DAC Playback Limiter Decay", WM8974_DACLIM1, 4, 15, 0), +SOC_SINGLE("DAC Playback Limiter Attack", WM8974_DACLIM1, 0, 15, 0), + +SOC_SINGLE("DAC Playback Limiter Threshold", WM8974_DACLIM2, 4, 7, 0), +SOC_SINGLE("DAC Playback Limiter Boost", WM8974_DACLIM2, 0, 15, 0), + +SOC_SINGLE("ALC Enable Switch", WM8974_ALC1, 8, 1, 0), +SOC_SINGLE("ALC Capture Max Gain", WM8974_ALC1, 3, 7, 0), +SOC_SINGLE("ALC Capture Min Gain", WM8974_ALC1, 0, 7, 0), + +SOC_SINGLE("ALC Capture ZC Switch", WM8974_ALC2, 8, 1, 0), +SOC_SINGLE("ALC Capture Hold", WM8974_ALC2, 4, 7, 0), +SOC_SINGLE("ALC Capture Target", WM8974_ALC2, 0, 15, 0), + +SOC_ENUM("ALC Capture Mode", wm8974_enum[13]), +SOC_SINGLE("ALC Capture Decay", WM8974_ALC3, 4, 15, 0), +SOC_SINGLE("ALC Capture Attack", WM8974_ALC3, 0, 15, 0), + +SOC_SINGLE("ALC Capture Noise Gate Switch", WM8974_NGATE, 3, 1, 0), +SOC_SINGLE("ALC Capture Noise Gate Threshold", WM8974_NGATE, 0, 7, 0), + +SOC_SINGLE("Capture PGA ZC Switch", WM8974_INPPGA, 7, 1, 0), +SOC_SINGLE("Capture PGA Volume", WM8974_INPPGA, 0, 63, 0), + +SOC_SINGLE("Speaker Playback ZC Switch", WM8974_SPKVOL, 7, 1, 0), +SOC_SINGLE("Speaker Playback Switch", WM8974_SPKVOL, 6, 1, 1), +SOC_SINGLE("Speaker Playback Volume", WM8974_SPKVOL, 0, 63, 0), + +SOC_SINGLE("Capture Boost(+20dB)", WM8974_ADCBOOST, 8, 1, 0), +SOC_SINGLE("Mono Playback Switch", WM8974_MONOMIX, 6, 1, 0), +}; + +/* add non dapm controls */ +static int wm8974_add_controls(struct snd_soc_codec *codec) +{ + int err, i; + + for (i = 0; i < ARRAY_SIZE(wm8974_snd_controls); i++) { + err = snd_ctl_add(codec->card, + snd_soc_cnew(&wm8974_snd_controls[i],codec, NULL)); + if (err < 0) + return err; + } + + return 0; +} + +/* Speaker Output Mixer */ +static const struct snd_kcontrol_new wm8974_speaker_mixer_controls[] = { +SOC_DAPM_SINGLE("Line Bypass Switch", WM8974_SPKMIX, 1, 1, 0), +SOC_DAPM_SINGLE("Aux Playback Switch", WM8974_SPKMIX, 5, 1, 0), +SOC_DAPM_SINGLE("PCM Playback Switch", WM8974_SPKMIX, 0, 1, 1), +}; + +/* Mono Output Mixer */ +static const struct snd_kcontrol_new wm8974_mono_mixer_controls[] = { +SOC_DAPM_SINGLE("Line Bypass Switch", WM8974_MONOMIX, 1, 1, 0), +SOC_DAPM_SINGLE("Aux Playback Switch", WM8974_MONOMIX, 2, 1, 0), +SOC_DAPM_SINGLE("PCM Playback Switch", WM8974_MONOMIX, 0, 1, 1), +}; + +/* AUX Input boost vol */ +static const struct snd_kcontrol_new wm8974_aux_boost_controls = +SOC_DAPM_SINGLE("Aux Volume", WM8974_ADCBOOST, 0, 7, 0); + +/* Mic Input boost vol */ +static const struct snd_kcontrol_new wm8974_mic_boost_controls = +SOC_DAPM_SINGLE("Mic Volume", WM8974_ADCBOOST, 4, 7, 0); + +/* Capture boost switch */ +static const struct snd_kcontrol_new wm8974_capture_boost_controls = +SOC_DAPM_SINGLE("Capture Boost Switch", WM8974_INPPGA, 6, 1, 0); + +/* Aux In to PGA */ +static const struct snd_kcontrol_new wm8974_aux_capture_boost_controls = +SOC_DAPM_SINGLE("Aux Capture Boost Switch", WM8974_INPPGA, 2, 1, 0); + +/* Mic P In to PGA */ +static const struct snd_kcontrol_new wm8974_micp_capture_boost_controls = +SOC_DAPM_SINGLE("Mic P Capture Boost Switch", WM8974_INPPGA, 0, 1, 0); + +/* Mic N In to PGA */ +static const struct snd_kcontrol_new wm8974_micn_capture_boost_controls = +SOC_DAPM_SINGLE("Mic N Capture Boost Switch", WM8974_INPPGA, 1, 1, 0); + +static const struct snd_soc_dapm_widget wm8974_dapm_widgets[] = { +SND_SOC_DAPM_MIXER("Speaker Mixer", WM8974_POWER3, 2, 0, + &wm8974_speaker_mixer_controls[0], + ARRAY_SIZE(wm8974_speaker_mixer_controls)), +SND_SOC_DAPM_MIXER("Mono Mixer", WM8974_POWER3, 3, 0, + &wm8974_mono_mixer_controls[0], + ARRAY_SIZE(wm8974_mono_mixer_controls)), +SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM8974_POWER3, 0, 0), +SND_SOC_DAPM_ADC("ADC", "HiFi Capture", WM8974_POWER3, 0, 0), +SND_SOC_DAPM_PGA("Aux Input", WM8974_POWER1, 6, 0, NULL, 0), +SND_SOC_DAPM_PGA("SpkN Out", WM8974_POWER3, 5, 0, NULL, 0), +SND_SOC_DAPM_PGA("SpkP Out", WM8974_POWER3, 6, 0, NULL, 0), +SND_SOC_DAPM_PGA("Mono Out", WM8974_POWER3, 7, 0, NULL, 0), +SND_SOC_DAPM_PGA("Mic PGA", WM8974_POWER2, 2, 0, NULL, 0), + +SND_SOC_DAPM_PGA("Aux Boost", SND_SOC_NOPM, 0, 0, + &wm8974_aux_boost_controls, 1), +SND_SOC_DAPM_PGA("Mic Boost", SND_SOC_NOPM, 0, 0, + &wm8974_mic_boost_controls, 1), +SND_SOC_DAPM_SWITCH("Capture Boost", SND_SOC_NOPM, 0, 0, + &wm8974_capture_boost_controls), + +SND_SOC_DAPM_MIXER("Boost Mixer", WM8974_POWER2, 4, 0, NULL, 0), + +SND_SOC_DAPM_MICBIAS("Mic Bias", WM8974_POWER1, 4, 0), + +SND_SOC_DAPM_INPUT("MICN"), +SND_SOC_DAPM_INPUT("MICP"), +SND_SOC_DAPM_INPUT("AUX"), +SND_SOC_DAPM_OUTPUT("MONOOUT"), +SND_SOC_DAPM_OUTPUT("SPKOUTP"), +SND_SOC_DAPM_OUTPUT("SPKOUTN"), +}; + +static const struct snd_soc_dapm_route audio_map[] = { + /* Mono output mixer */ + {"Mono Mixer", "PCM Playback Switch", "DAC"}, + {"Mono Mixer", "Aux Playback Switch", "Aux Input"}, + {"Mono Mixer", "Line Bypass Switch", "Boost Mixer"}, + + /* Speaker output mixer */ + {"Speaker Mixer", "PCM Playback Switch", "DAC"}, + {"Speaker Mixer", "Aux Playback Switch", "Aux Input"}, + {"Speaker Mixer", "Line Bypass Switch", "Boost Mixer"}, + + /* Outputs */ + {"Mono Out", NULL, "Mono Mixer"}, + {"MONOOUT", NULL, "Mono Out"}, + {"SpkN Out", NULL, "Speaker Mixer"}, + {"SpkP Out", NULL, "Speaker Mixer"}, + {"SPKOUTN", NULL, "SpkN Out"}, + {"SPKOUTP", NULL, "SpkP Out"}, + + /* Boost Mixer */ + {"Boost Mixer", NULL, "ADC"}, + {"Capture Boost Switch", "Aux Capture Boost Switch", "AUX"}, + {"Aux Boost", "Aux Volume", "Boost Mixer"}, + {"Capture Boost", "Capture Switch", "Boost Mixer"}, + {"Mic Boost", "Mic Volume", "Boost Mixer"}, + + /* Inputs */ + {"MICP", NULL, "Mic Boost"}, + {"MICN", NULL, "Mic PGA"}, + {"Mic PGA", NULL, "Capture Boost"}, + {"AUX", NULL, "Aux Input"}, +}; + +static int wm8974_add_widgets(struct snd_soc_codec *codec) +{ + snd_soc_dapm_new_controls(codec, wm8974_dapm_widgets, + ARRAY_SIZE(wm8974_dapm_widgets)); + + snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + + snd_soc_dapm_new_widgets(codec); + return 0; +} + +struct pll_ { + unsigned int in_hz, out_hz; + unsigned int pre:4; /* prescale - 1 */ + unsigned int n:4; + unsigned int k; +}; + +static struct pll_ pll[] = { + {12000000, 11289600, 0, 7, 0x86c220}, + {12000000, 12288000, 0, 8, 0x3126e8}, + {13000000, 11289600, 0, 6, 0xf28bd4}, + {13000000, 12288000, 0, 7, 0x8fd525}, + {12288000, 11289600, 0, 7, 0x59999a}, + {11289600, 12288000, 0, 8, 0x80dee9}, + /* liam - add more entries */ +}; + +static int wm8974_set_dai_pll(struct snd_soc_dai *codec_dai, + int pll_id, unsigned int freq_in, unsigned int freq_out) +{ + struct snd_soc_codec *codec = codec_dai->codec; + int i; + u16 reg; + + if(freq_in == 0 || freq_out == 0) { + reg = wm8974_read_reg_cache(codec, WM8974_POWER1); + wm8974_write(codec, WM8974_POWER1, reg & 0x1df); + return 0; + } + + for(i = 0; i < ARRAY_SIZE(pll); i++) { + if (freq_in == pll[i].in_hz && freq_out == pll[i].out_hz) { + wm8974_write(codec, WM8974_PLLN, (pll[i].pre << 4) | pll[i].n); + wm8974_write(codec, WM8974_PLLK1, pll[i].k >> 18); + wm8974_write(codec, WM8974_PLLK1, (pll[i].k >> 9) && 0x1ff); + wm8974_write(codec, WM8974_PLLK1, pll[i].k && 0x1ff); + reg = wm8974_read_reg_cache(codec, WM8974_POWER1); + wm8974_write(codec, WM8974_POWER1, reg | 0x020); + return 0; + } + } + return -EINVAL; +} + +/* + * Configure WM8974 clock dividers. + */ +static int wm8974_set_dai_clkdiv(struct snd_soc_dai *codec_dai, + int div_id, int div) +{ + struct snd_soc_codec *codec = codec_dai->codec; + u16 reg; + + switch (div_id) { + case WM8974_OPCLKDIV: + reg = wm8974_read_reg_cache(codec, WM8974_GPIO & 0x1cf); + wm8974_write(codec, WM8974_GPIO, reg | div); + break; + case WM8974_MCLKDIV: + reg = wm8974_read_reg_cache(codec, WM8974_CLOCK & 0x1f); + wm8974_write(codec, WM8974_CLOCK, reg | div); + break; + case WM8974_ADCCLK: + reg = wm8974_read_reg_cache(codec, WM8974_ADC & 0x1f7); + wm8974_write(codec, WM8974_ADC, reg | div); + break; + case WM8974_DACCLK: + reg = wm8974_read_reg_cache(codec, WM8974_DAC & 0x1f7); + wm8974_write(codec, WM8974_DAC, reg | div); + break; + case WM8974_BCLKDIV: + reg = wm8974_read_reg_cache(codec, WM8974_CLOCK & 0x1e3); + wm8974_write(codec, WM8974_CLOCK, reg | div); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int wm8974_set_dai_fmt(struct snd_soc_dai *codec_dai, + unsigned int fmt) +{ + struct snd_soc_codec *codec = codec_dai->codec; + u16 iface = 0; + u16 clk = wm8974_read_reg_cache(codec, WM8974_CLOCK) & 0x1fe; + + /* set master/slave audio interface */ + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + clk |= 0x0001; + break; + case SND_SOC_DAIFMT_CBS_CFS: + break; + default: + return -EINVAL; + } + + /* interface format */ + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + iface |= 0x0010; + break; + case SND_SOC_DAIFMT_RIGHT_J: + break; + case SND_SOC_DAIFMT_LEFT_J: + iface |= 0x0008; + break; + case SND_SOC_DAIFMT_DSP_A: + iface |= 0x00018; + break; + default: + return -EINVAL; + } + + /* clock inversion */ + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + case SND_SOC_DAIFMT_IB_IF: + iface |= 0x0180; + break; + case SND_SOC_DAIFMT_IB_NF: + iface |= 0x0100; + break; + case SND_SOC_DAIFMT_NB_IF: + iface |= 0x0080; + break; + default: + return -EINVAL; + } + + wm8974_write(codec, WM8974_IFACE, iface); + wm8974_write(codec, WM8974_CLOCK, clk); + return 0; +} + +static int wm8974_pcm_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->codec; + u16 iface = wm8974_read_reg_cache(codec, WM8974_IFACE) & 0x19f; + u16 adn = wm8974_read_reg_cache(codec, WM8974_ADD) & 0x1f1; + + /* bit size */ + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + break; + case SNDRV_PCM_FORMAT_S20_3LE: + iface |= 0x0020; + break; + case SNDRV_PCM_FORMAT_S24_LE: + iface |= 0x0040; + break; + case SNDRV_PCM_FORMAT_S32_LE: + iface |= 0x0060; + break; + } + + /* filter coefficient */ + switch (params_rate(params)) { + case SNDRV_PCM_RATE_8000: + adn |= 0x5 << 1; + break; + case SNDRV_PCM_RATE_11025: + adn |= 0x4 << 1; + break; + case SNDRV_PCM_RATE_16000: + adn |= 0x3 << 1; + break; + case SNDRV_PCM_RATE_22050: + adn |= 0x2 << 1; + break; + case SNDRV_PCM_RATE_32000: + adn |= 0x1 << 1; + break; + case SNDRV_PCM_RATE_44100: + break; + } + + wm8974_write(codec, WM8974_IFACE, iface); + wm8974_write(codec, WM8974_ADD, adn); + return 0; +} + +static int wm8974_mute(struct snd_soc_dai *dai, int mute) +{ + struct snd_soc_codec *codec = dai->codec; + u16 mute_reg = wm8974_read_reg_cache(codec, WM8974_DAC) & 0xffbf; + + if(mute) + wm8974_write(codec, WM8974_DAC, mute_reg | 0x40); + else + wm8974_write(codec, WM8974_DAC, mute_reg); + return 0; +} + +/* liam need to make this lower power with dapm */ +static int wm8974_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level) +{ + switch (level) { + case SND_SOC_BIAS_ON: + wm8974_write(codec, WM8974_POWER1, 0x1ff); + wm8974_write(codec, WM8974_POWER2, 0x1ff); + wm8974_write(codec, WM8974_POWER3, 0x1ff); + break; + case SND_SOC_BIAS_PREPARE: + break; + case SND_SOC_BIAS_STANDBY: + break; + case SND_SOC_BIAS_OFF: + wm8974_write(codec, WM8974_POWER1, 0x0); + wm8974_write(codec, WM8974_POWER2, 0x0); + wm8974_write(codec, WM8974_POWER3, 0x0); + break; + } + codec->bias_level = level; + return 0; +} + +#define WM8974_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ + SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \ + SNDRV_PCM_RATE_48000) + +#define WM8974_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ + SNDRV_PCM_FMTBIT_S24_LE) + +struct snd_soc_dai wm8974_dai = { + .name = "WM8974 HiFi", + .playback = { + .stream_name = "Playback", + .channels_min = 1, + .channels_max = 1, + .rates = WM8974_RATES, + .formats = WM8974_FORMATS,}, + .capture = { + .stream_name = "Capture", + .channels_min = 1, + .channels_max = 1, + .rates = WM8974_RATES, + .formats = WM8974_FORMATS,}, + .ops = { + .hw_params = wm8974_pcm_hw_params, + .digital_mute = wm8974_mute, + .set_fmt = wm8974_set_dai_fmt, + .set_clkdiv = wm8974_set_dai_clkdiv, + .set_pll = wm8974_set_dai_pll, + }, +}; +EXPORT_SYMBOL_GPL(wm8974_dai); + +static int wm8974_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + + wm8974_set_bias_level(codec, SND_SOC_BIAS_OFF); + return 0; +} + +static int wm8974_resume(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + int i; + u8 data[2]; + u16 *cache = codec->reg_cache; + + /* Sync reg_cache with the hardware */ + for (i = 0; i < ARRAY_SIZE(wm8974_reg); i++) { + data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001); + data[1] = cache[i] & 0x00ff; + codec->hw_write(codec->control_data, data, 2); + } + wm8974_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + wm8974_set_bias_level(codec, codec->suspend_bias_level); + return 0; +} + +/* + * initialise the WM8974 driver + * register the mixer and dsp interfaces with the kernel + */ +static int wm8974_init(struct snd_soc_device *socdev) +{ + struct snd_soc_codec *codec = socdev->codec; + int ret = 0; + + codec->name = "WM8974"; + codec->owner = THIS_MODULE; + codec->read = wm8974_read_reg_cache; + codec->write = wm8974_write; + codec->set_bias_level = wm8974_set_bias_level; + codec->dai = &wm8974_dai; + codec->num_dai = 1; + codec->reg_cache_size = ARRAY_SIZE(wm8974_reg); + codec->reg_cache = kmemdup(wm8974_reg, sizeof(wm8974_reg), GFP_KERNEL); + + if (codec->reg_cache == NULL) + return -ENOMEM; + + wm8974_reset(codec); + + /* register pcms */ + ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); + if(ret < 0) { + printk(KERN_ERR "wm8974: failed to create pcms\n"); + goto pcm_err; + } + + /* power on device */ + wm8974_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + wm8974_add_controls(codec); + wm8974_add_widgets(codec); + ret = snd_soc_init_card(socdev); + if (ret < 0) { + printk(KERN_ERR "wm8974: failed to register card\n"); + goto card_err; + } + return ret; + +card_err: + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); +pcm_err: + kfree(codec->reg_cache); + return ret; +} + +static struct snd_soc_device *wm8974_socdev; + +#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE) + +/* + * WM8974 2 wire address is 0x1a + */ +#define I2C_DRIVERID_WM8974 0xfefe /* liam - need a proper id */ + +static unsigned short normal_i2c[] = { 0, I2C_CLIENT_END }; + +/* Magic definition of all other variables and things */ +I2C_CLIENT_INSMOD; + +static struct i2c_driver wm8974_i2c_driver; +static struct i2c_client client_template; + +/* If the i2c layer weren't so broken, we could pass this kind of data + around */ + +static int wm8974_codec_probe(struct i2c_adapter *adap, int addr, int kind) +{ + struct snd_soc_device *socdev = wm8974_socdev; + struct wm8974_setup_data *setup = socdev->codec_data; + struct snd_soc_codec *codec = socdev->codec; + struct i2c_client *i2c; + int ret; + + if (addr != setup->i2c_address) + return -ENODEV; + + client_template.adapter = adap; + client_template.addr = addr; + + i2c = kmemdup(&client_template, sizeof(client_template), GFP_KERNEL); + if (i2c == NULL) { + kfree(codec); + return -ENOMEM; + } + i2c_set_clientdata(i2c, codec); + codec->control_data = i2c; + + ret = i2c_attach_client(i2c); + if (ret < 0) { + pr_err("failed to attach codec at addr %x\n", addr); + goto err; + } + + ret = wm8974_init(socdev); + if (ret < 0) { + pr_err("failed to initialise WM8974\n"); + goto err; + } + return ret; + +err: + kfree(codec); + kfree(i2c); + return ret; +} + +static int wm8974_i2c_detach(struct i2c_client *client) +{ + struct snd_soc_codec *codec = i2c_get_clientdata(client); + i2c_detach_client(client); + kfree(codec->reg_cache); + kfree(client); + return 0; +} + +static int wm8974_i2c_attach(struct i2c_adapter *adap) +{ + return i2c_probe(adap, &addr_data, wm8974_codec_probe); +} + +/* corgi i2c codec control layer */ +static struct i2c_driver wm8974_i2c_driver = { + .driver = { + .name = "WM8974 I2C Codec", + .owner = THIS_MODULE, + }, + .id = I2C_DRIVERID_WM8974, + .attach_adapter = wm8974_i2c_attach, + .detach_client = wm8974_i2c_detach, + .command = NULL, +}; + +static struct i2c_client client_template = { + .name = "WM8974", + .driver = &wm8974_i2c_driver, +}; +#endif + +static int wm8974_probe(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct wm8974_setup_data *setup; + struct snd_soc_codec *codec; + int ret = 0; + + pr_info("WM8974 Audio Codec %s", WM8974_VERSION); + + setup = socdev->codec_data; + codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); + if (codec == NULL) + return -ENOMEM; + + socdev->codec = codec; + mutex_init(&codec->mutex); + INIT_LIST_HEAD(&codec->dapm_widgets); + INIT_LIST_HEAD(&codec->dapm_paths); + + wm8974_socdev = socdev; +#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE) + if (setup->i2c_address) { + normal_i2c[0] = setup->i2c_address; + codec->hw_write = (hw_write_t)i2c_master_send; + ret = i2c_add_driver(&wm8974_i2c_driver); + if (ret != 0) + printk(KERN_ERR "can't add i2c driver"); + } +#else + /* Add other interfaces here */ +#endif + return ret; +} + +/* power down chip */ +static int wm8974_remove(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + + if (codec->control_data) + wm8974_set_bias_level(codec, SND_SOC_BIAS_OFF); + + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); +#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE) + i2c_del_driver(&wm8974_i2c_driver); +#endif + kfree(codec); + + return 0; +} + +struct snd_soc_codec_device soc_codec_dev_wm8974 = { + .probe = wm8974_probe, + .remove = wm8974_remove, + .suspend = wm8974_suspend, + .resume = wm8974_resume, +}; +EXPORT_SYMBOL_GPL(soc_codec_dev_wm8974); + +static int __init wm8974_modinit(void) +{ + return snd_soc_register_dai(&wm8974_dai); +} +module_init(wm8974_modinit); + +static void __exit wm8974_exit(void) +{ + snd_soc_unregister_dai(&wm8974_dai); +} +module_exit(wm8974_exit); + +MODULE_DESCRIPTION("ASoC WM8974 driver"); +MODULE_AUTHOR("Liam Girdwood"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/wm8974.h b/sound/soc/codecs/wm8974.h new file mode 100644 index 0000000..0f5172e --- /dev/null +++ b/sound/soc/codecs/wm8974.h @@ -0,0 +1,104 @@ +/* + * wm8974.h -- WM8974 Soc Audio driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _WM8974_H +#define _WM8974_H + +/* WM8974 register space */ + +#define WM8974_RESET 0x0 +#define WM8974_POWER1 0x1 +#define WM8974_POWER2 0x2 +#define WM8974_POWER3 0x3 +#define WM8974_IFACE 0x4 +#define WM8974_COMP 0x5 +#define WM8974_CLOCK 0x6 +#define WM8974_ADD 0x7 +#define WM8974_GPIO 0x8 +#define WM8974_DAC 0xa +#define WM8974_DACVOL 0xb +#define WM8974_ADC 0xe +#define WM8974_ADCVOL 0xf +#define WM8974_EQ1 0x12 +#define WM8974_EQ2 0x13 +#define WM8974_EQ3 0x14 +#define WM8974_EQ4 0x15 +#define WM8974_EQ5 0x16 +#define WM8974_DACLIM1 0x18 +#define WM8974_DACLIM2 0x19 +#define WM8974_NOTCH1 0x1b +#define WM8974_NOTCH2 0x1c +#define WM8974_NOTCH3 0x1d +#define WM8974_NOTCH4 0x1e +#define WM8974_ALC1 0x20 +#define WM8974_ALC2 0x21 +#define WM8974_ALC3 0x22 +#define WM8974_NGATE 0x23 +#define WM8974_PLLN 0x24 +#define WM8974_PLLK1 0x25 +#define WM8974_PLLK2 0x26 +#define WM8974_PLLK3 0x27 +#define WM8974_ATTEN 0x28 +#define WM8974_INPUT 0x2c +#define WM8974_INPPGA 0x2d +#define WM8974_ADCBOOST 0x2f +#define WM8974_OUTPUT 0x31 +#define WM8974_SPKMIX 0x32 +#define WM8974_SPKVOL 0x36 +#define WM8974_MONOMIX 0x38 + +#define WM8974_CACHEREGNUM 57 + +/* Clock divider Id's */ +#define WM8974_OPCLKDIV 0 +#define WM8974_MCLKDIV 1 +#define WM8974_ADCCLK 2 +#define WM8974_DACCLK 3 +#define WM8974_BCLKDIV 4 + +/* DAC clock dividers */ +#define WM8974_DACCLK_F2 (1 << 3) +#define WM8974_DACCLK_F4 (0 << 3) + +/* ADC clock dividers */ +#define WM8974_ADCCLK_F2 (1 << 3) +#define WM8974_ADCCLK_F4 (0 << 3) + +/* PLL Out dividers */ +#define WM8974_OPCLKDIV_1 (0 << 4) +#define WM8974_OPCLKDIV_2 (1 << 4) +#define WM8974_OPCLKDIV_3 (2 << 4) +#define WM8974_OPCLKDIV_4 (3 << 4) + +/* BCLK clock dividers */ +#define WM8974_BCLKDIV_1 (0 << 2) +#define WM8974_BCLKDIV_2 (1 << 2) +#define WM8974_BCLKDIV_4 (2 << 2) +#define WM8974_BCLKDIV_8 (3 << 2) +#define WM8974_BCLKDIV_16 (4 << 2) +#define WM8974_BCLKDIV_32 (5 << 2) + +/* MCLK clock dividers */ +#define WM8974_MCLKDIV_1 (0 << 5) +#define WM8974_MCLKDIV_1_5 (1 << 5) +#define WM8974_MCLKDIV_2 (2 << 5) +#define WM8974_MCLKDIV_3 (3 << 5) +#define WM8974_MCLKDIV_4 (4 << 5) +#define WM8974_MCLKDIV_6 (5 << 5) +#define WM8974_MCLKDIV_8 (6 << 5) +#define WM8974_MCLKDIV_12 (7 << 5) + + +struct wm8974_setup_data { + unsigned short i2c_address; +}; + +extern struct snd_soc_dai wm8974_dai; +extern struct snd_soc_codec_device soc_codec_dev_wm8974; + +#endif diff --git a/sound/soc/codecs/wm8976.c b/sound/soc/codecs/wm8976.c new file mode 100644 index 0000000..4af62ab --- /dev/null +++ b/sound/soc/codecs/wm8976.c @@ -0,0 +1,885 @@ +/* + * wm8976.c -- WM8976 ALSA Soc Audio driver + * + * Copyright 2006 Wolfson Microelectronics PLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "wm8976.h" + +#define AUDIO_NAME "wm8976" +#define WM8976_VERSION "0.4" + + +struct snd_soc_codec_device soc_codec_dev_wm8976; + +/* + * wm8976 register cache + * We can't read the WM8976 register space when we are + * using 2 wire for device control, so we cache them instead. + */ +static const u16 wm8976_reg[WM8976_CACHEREGNUM] = { + 0x0000, 0x0000, 0x0000, 0x0000, + 0x0050, 0x0000, 0x0140, 0x0000, + 0x0000, 0x0000, 0x0000, 0x00ff, + 0x00ff, 0x0000, 0x0100, 0x00ff, + 0x00ff, 0x0000, 0x012c, 0x002c, + 0x002c, 0x002c, 0x002c, 0x0000, + 0x0032, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, + 0x0038, 0x000b, 0x0032, 0x0000, + 0x0008, 0x000c, 0x0093, 0x00e9, + 0x0000, 0x0000, 0x0000, 0x0000, + 0x0033, 0x0010, 0x0010, 0x0100, + 0x0100, 0x0002, 0x0001, 0x0001, + 0x0039, 0x0039, 0x0039, 0x0039, + 0x0001, 0x0001, +}; + +/* + * read wm8976 register cache + */ +static inline unsigned int wm8976_read_reg_cache(struct snd_soc_codec *codec, + unsigned int reg) +{ + u16 *cache = codec->reg_cache; + if (reg == WM8976_RESET) + return 0; + if (reg >= WM8976_CACHEREGNUM) + return -1; + return cache[reg]; +} + +/* + * write wm8976 register cache + */ +static inline void wm8976_write_reg_cache(struct snd_soc_codec *codec, + u16 reg, unsigned int value) +{ + u16 *cache = codec->reg_cache; + if (reg >= WM8976_CACHEREGNUM) + return; + cache[reg] = value; +} + +/* + * write to the WM8976 register space + */ +static int wm8976_write(struct snd_soc_codec *codec, unsigned int reg, + unsigned int value) +{ + u8 data[2]; + + /* data is + * D15..D9 WM8976 register offset + * D8...D0 register data + */ + data[0] = (reg << 1) | ((value >> 8) & 0x0001); + data[1] = value & 0x00ff; + + wm8976_write_reg_cache (codec, reg, value); + if (codec->hw_write(codec->control_data, data, 2) == 2) + return 0; + else + return -1; +} + +#define wm8976_reset(c) wm8976_write(c, WM8976_RESET, 0) + +static const char *wm8976_companding[] = {"Off", "NC", "u-law", "A-law" }; +static const char *wm8976_deemp[] = {"None", "32kHz", "44.1kHz", "48kHz" }; +static const char *wm8976_eqmode[] = {"Capture", "Playback" }; +static const char *wm8976_bw[] = {"Narrow", "Wide" }; +static const char *wm8976_eq1[] = {"80Hz", "105Hz", "135Hz", "175Hz" }; +static const char *wm8976_eq2[] = {"230Hz", "300Hz", "385Hz", "500Hz" }; +static const char *wm8976_eq3[] = {"650Hz", "850Hz", "1.1kHz", "1.4kHz" }; +static const char *wm8976_eq4[] = {"1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz" }; +static const char *wm8976_eq5[] = {"5.3kHz", "6.9kHz", "9kHz", "11.7kHz" }; +static const char *wm8976_alc[] = + {"ALC both on", "ALC left only", "ALC right only", "Limiter" }; + +static const struct soc_enum wm8976_enum[] = { + SOC_ENUM_SINGLE(WM8976_COMP, 1, 4, wm8976_companding), /* adc */ + SOC_ENUM_SINGLE(WM8976_COMP, 3, 4, wm8976_companding), /* dac */ + SOC_ENUM_SINGLE(WM8976_DAC, 4, 4, wm8976_deemp), + SOC_ENUM_SINGLE(WM8976_EQ1, 8, 2, wm8976_eqmode), + + SOC_ENUM_SINGLE(WM8976_EQ1, 5, 4, wm8976_eq1), + SOC_ENUM_SINGLE(WM8976_EQ2, 8, 2, wm8976_bw), + SOC_ENUM_SINGLE(WM8976_EQ2, 5, 4, wm8976_eq2), + SOC_ENUM_SINGLE(WM8976_EQ3, 8, 2, wm8976_bw), + + SOC_ENUM_SINGLE(WM8976_EQ3, 5, 4, wm8976_eq3), + SOC_ENUM_SINGLE(WM8976_EQ4, 8, 2, wm8976_bw), + SOC_ENUM_SINGLE(WM8976_EQ4, 5, 4, wm8976_eq4), + SOC_ENUM_SINGLE(WM8976_EQ5, 8, 2, wm8976_bw), + + SOC_ENUM_SINGLE(WM8976_EQ5, 5, 4, wm8976_eq5), + SOC_ENUM_SINGLE(WM8976_ALC3, 8, 2, wm8976_alc), +}; + +static const struct snd_kcontrol_new wm8976_snd_controls[] = { +SOC_SINGLE("Digital Loopback Switch", WM8976_COMP, 0, 1, 0), + +SOC_ENUM("ADC Companding", wm8976_enum[0]), +SOC_ENUM("DAC Companding", wm8976_enum[1]), + +SOC_SINGLE("Jack Detection Enable", WM8976_JACK1, 6, 1, 0), + +SOC_DOUBLE("DAC Inversion Switch", WM8976_DAC, 0, 1, 1, 0), + +SOC_DOUBLE_R("Headphone Playback Volume", WM8976_DACVOLL, WM8976_DACVOLR, 0, 127, 0), + +SOC_SINGLE("High Pass Filter Switch", WM8976_ADC, 8, 1, 0), +SOC_SINGLE("High Pass Filter Switch", WM8976_ADC, 8, 1, 0), +SOC_SINGLE("High Pass Cut Off", WM8976_ADC, 4, 7, 0), + +SOC_DOUBLE("ADC Inversion Switch", WM8976_ADC, 0, 1, 1, 0), + +SOC_SINGLE("Capture Volume", WM8976_ADCVOL, 0, 127, 0), + +SOC_ENUM("Equaliser Function", wm8976_enum[3]), +SOC_ENUM("EQ1 Cut Off", wm8976_enum[4]), +SOC_SINGLE("EQ1 Volume", WM8976_EQ1, 0, 31, 1), + +SOC_ENUM("Equaliser EQ2 Bandwith", wm8976_enum[5]), +SOC_ENUM("EQ2 Cut Off", wm8976_enum[6]), +SOC_SINGLE("EQ2 Volume", WM8976_EQ2, 0, 31, 1), + +SOC_ENUM("Equaliser EQ3 Bandwith", wm8976_enum[7]), +SOC_ENUM("EQ3 Cut Off", wm8976_enum[8]), +SOC_SINGLE("EQ3 Volume", WM8976_EQ3, 0, 31, 1), + +SOC_ENUM("Equaliser EQ4 Bandwith", wm8976_enum[9]), +SOC_ENUM("EQ4 Cut Off", wm8976_enum[10]), +SOC_SINGLE("EQ4 Volume", WM8976_EQ4, 0, 31, 1), + +SOC_ENUM("Equaliser EQ5 Bandwith", wm8976_enum[11]), +SOC_ENUM("EQ5 Cut Off", wm8976_enum[12]), +SOC_SINGLE("EQ5 Volume", WM8976_EQ5, 0, 31, 1), + +SOC_SINGLE("DAC Playback Limiter Switch", WM8976_DACLIM1, 8, 1, 0), +SOC_SINGLE("DAC Playback Limiter Decay", WM8976_DACLIM1, 4, 15, 0), +SOC_SINGLE("DAC Playback Limiter Attack", WM8976_DACLIM1, 0, 15, 0), + +SOC_SINGLE("DAC Playback Limiter Threshold", WM8976_DACLIM2, 4, 7, 0), +SOC_SINGLE("DAC Playback Limiter Boost", WM8976_DACLIM2, 0, 15, 0), + +SOC_SINGLE("ALC Enable Switch", WM8976_ALC1, 8, 1, 0), +SOC_SINGLE("ALC Capture Max Gain", WM8976_ALC1, 3, 7, 0), +SOC_SINGLE("ALC Capture Min Gain", WM8976_ALC1, 0, 7, 0), + +SOC_SINGLE("ALC Capture ZC Switch", WM8976_ALC2, 8, 1, 0), +SOC_SINGLE("ALC Capture Hold", WM8976_ALC2, 4, 7, 0), +SOC_SINGLE("ALC Capture Target", WM8976_ALC2, 0, 15, 0), + +SOC_ENUM("ALC Capture Mode", wm8976_enum[13]), +SOC_SINGLE("ALC Capture Decay", WM8976_ALC3, 4, 15, 0), +SOC_SINGLE("ALC Capture Attack", WM8976_ALC3, 0, 15, 0), + +SOC_SINGLE("ALC Capture Noise Gate Switch", WM8976_NGATE, 3, 1, 0), +SOC_SINGLE("ALC Capture Noise Gate Threshold", WM8976_NGATE, 0, 7, 0), + +SOC_SINGLE("Capture PGA ZC Switch", WM8976_INPPGA, 7, 1, 0), +SOC_SINGLE("Capture PGA Volume", WM8976_INPPGA, 0, 63, 0), + +SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8976_HPVOLL, WM8976_HPVOLR, 7, 1, 0), +SOC_DOUBLE_R("Headphone Playback Switch", WM8976_HPVOLL, WM8976_HPVOLR, 6, 1, 1), +SOC_DOUBLE_R("Headphone Playback Volume", WM8976_HPVOLL, WM8976_HPVOLR, 0, 63, 0), + +SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8976_SPKVOLL, WM8976_SPKVOLR, 7, 1, 0), +SOC_DOUBLE_R("Speaker Playback Switch", WM8976_SPKVOLL, WM8976_SPKVOLR, 6, 1, 1), +SOC_DOUBLE_R("Speaker Playback Volume", WM8976_SPKVOLL, WM8976_SPKVOLR, 0, 63, 0), + +SOC_SINGLE("Capture Boost(+20dB)", WM8976_ADCBOOST, 8, 1, 0), +}; + +/* add non dapm controls */ +static int wm8976_add_controls(struct snd_soc_codec *codec) +{ + int err, i; + + for (i = 0; i < ARRAY_SIZE(wm8976_snd_controls); i++) { + err = snd_ctl_add(codec->card, + snd_soc_cnew(&wm8976_snd_controls[i],codec, NULL)); + if (err < 0) + return err; + } + + return 0; +} + +/* Left Output Mixer */ +static const struct snd_kcontrol_new wm8976_left_mixer_controls[] = { +SOC_DAPM_SINGLE("Right PCM Playback Switch", WM8976_OUTPUT, 6, 1, 1), +SOC_DAPM_SINGLE("Left PCM Playback Switch", WM8976_MIXL, 0, 1, 1), +SOC_DAPM_SINGLE("Line Bypass Switch", WM8976_MIXL, 1, 1, 0), +SOC_DAPM_SINGLE("Aux Playback Switch", WM8976_MIXL, 5, 1, 0), +}; + +/* Right Output Mixer */ +static const struct snd_kcontrol_new wm8976_right_mixer_controls[] = { +SOC_DAPM_SINGLE("Left PCM Playback Switch", WM8976_OUTPUT, 5, 1, 1), +SOC_DAPM_SINGLE("Right PCM Playback Switch", WM8976_MIXR, 0, 1, 1), +SOC_DAPM_SINGLE("Line Bypass Switch", WM8976_MIXR, 1, 1, 0), +SOC_DAPM_SINGLE("Aux Playback Switch", WM8976_MIXR, 5, 1, 0), +}; + +/* Left AUX Input boost vol */ +static const struct snd_kcontrol_new wm8976_laux_boost_controls = +SOC_DAPM_SINGLE("Aux Volume", WM8976_ADCBOOST, 0, 3, 0); + +/* Left Input boost vol */ +static const struct snd_kcontrol_new wm8976_lmic_boost_controls = +SOC_DAPM_SINGLE("Input Volume", WM8976_ADCBOOST, 4, 3, 0); + +/* Left Aux In to PGA */ +static const struct snd_kcontrol_new wm8976_laux_capture_boost_controls = +SOC_DAPM_SINGLE("Capture Switch", WM8976_ADCBOOST, 8, 1, 0); + +/* Left Input P In to PGA */ +static const struct snd_kcontrol_new wm8976_lmicp_capture_boost_controls = +SOC_DAPM_SINGLE("Input P Capture Boost Switch", WM8976_INPUT, 0, 1, 0); + +/* Left Input N In to PGA */ +static const struct snd_kcontrol_new wm8976_lmicn_capture_boost_controls = +SOC_DAPM_SINGLE("Input N Capture Boost Switch", WM8976_INPUT, 1, 1, 0); + +// TODO Widgets +static const struct snd_soc_dapm_widget wm8976_dapm_widgets[] = { +#if 0 +//SND_SOC_DAPM_MUTE("Mono Mute", WM8976_MONOMIX, 6, 0), +//SND_SOC_DAPM_MUTE("Speaker Mute", WM8976_SPKMIX, 6, 0), + +SND_SOC_DAPM_MIXER("Speaker Mixer", WM8976_POWER3, 2, 0, + &wm8976_speaker_mixer_controls[0], + ARRAY_SIZE(wm8976_speaker_mixer_controls)), +SND_SOC_DAPM_MIXER("Mono Mixer", WM8976_POWER3, 3, 0, + &wm8976_mono_mixer_controls[0], + ARRAY_SIZE(wm8976_mono_mixer_controls)), +SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM8976_POWER3, 0, 0), +SND_SOC_DAPM_ADC("ADC", "HiFi Capture", WM8976_POWER3, 0, 0), +SND_SOC_DAPM_PGA("Aux Input", WM8976_POWER1, 6, 0, NULL, 0), +SND_SOC_DAPM_PGA("SpkN Out", WM8976_POWER3, 5, 0, NULL, 0), +SND_SOC_DAPM_PGA("SpkP Out", WM8976_POWER3, 6, 0, NULL, 0), +SND_SOC_DAPM_PGA("Mono Out", WM8976_POWER3, 7, 0, NULL, 0), +SND_SOC_DAPM_PGA("Mic PGA", WM8976_POWER2, 2, 0, NULL, 0), + +SND_SOC_DAPM_PGA("Aux Boost", SND_SOC_NOPM, 0, 0, + &wm8976_aux_boost_controls, 1), +SND_SOC_DAPM_PGA("Mic Boost", SND_SOC_NOPM, 0, 0, + &wm8976_mic_boost_controls, 1), +SND_SOC_DAPM_SWITCH("Capture Boost", SND_SOC_NOPM, 0, 0, + &wm8976_capture_boost_controls), + +SND_SOC_DAPM_MIXER("Boost Mixer", WM8976_POWER2, 4, 0, NULL, 0), + +SND_SOC_DAPM_MICBIAS("Mic Bias", WM8976_POWER1, 4, 0), + +SND_SOC_DAPM_INPUT("MICN"), +SND_SOC_DAPM_INPUT("MICP"), +SND_SOC_DAPM_INPUT("AUX"), +SND_SOC_DAPM_OUTPUT("MONOOUT"), +SND_SOC_DAPM_OUTPUT("SPKOUTP"), +SND_SOC_DAPM_OUTPUT("SPKOUTN"), +#endif +}; + +static const struct snd_soc_dapm_route audio_map[] = { + /* Mono output mixer */ + {"Mono Mixer", "PCM Playback Switch", "DAC"}, + {"Mono Mixer", "Aux Playback Switch", "Aux Input"}, + {"Mono Mixer", "Line Bypass Switch", "Boost Mixer"}, + + /* Speaker output mixer */ + {"Speaker Mixer", "PCM Playback Switch", "DAC"}, + {"Speaker Mixer", "Aux Playback Switch", "Aux Input"}, + {"Speaker Mixer", "Line Bypass Switch", "Boost Mixer"}, + + /* Outputs */ + {"Mono Out", NULL, "Mono Mixer"}, + {"MONOOUT", NULL, "Mono Out"}, + {"SpkN Out", NULL, "Speaker Mixer"}, + {"SpkP Out", NULL, "Speaker Mixer"}, + {"SPKOUTN", NULL, "SpkN Out"}, + {"SPKOUTP", NULL, "SpkP Out"}, + + /* Boost Mixer */ + {"Boost Mixer", NULL, "ADC"}, + {"Capture Boost Switch", "Aux Capture Boost Switch", "AUX"}, + {"Aux Boost", "Aux Volume", "Boost Mixer"}, + {"Capture Boost", "Capture Switch", "Boost Mixer"}, + {"Mic Boost", "Mic Volume", "Boost Mixer"}, + + /* Inputs */ + {"MICP", NULL, "Mic Boost"}, + {"MICN", NULL, "Mic PGA"}, + {"Mic PGA", NULL, "Capture Boost"}, + {"AUX", NULL, "Aux Input"}, +}; + +static int wm8976_add_widgets(struct snd_soc_codec *codec) +{ + snd_soc_dapm_new_controls(codec, wm8976_dapm_widgets, + ARRAY_SIZE(wm8976_dapm_widgets)); + + snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + + snd_soc_dapm_new_widgets(codec); + return 0; +} + +struct _pll_div { + unsigned int pre:4; /* prescale - 1 */ + unsigned int n:4; + unsigned int k; +}; + +static struct _pll_div pll_div; + +/* The size in bits of the pll divide multiplied by 10 + * to allow rounding later */ +#define FIXED_PLL_SIZE ((1 << 24) * 10) + +static void pll_factors(unsigned int target, unsigned int source) +{ + unsigned long long Kpart; + unsigned int K, Ndiv, Nmod; + + Ndiv = target / source; + if (Ndiv < 6) { + source >>= 1; + pll_div.pre = 1; + Ndiv = target / source; + } else + pll_div.pre = 0; + + if ((Ndiv < 6) || (Ndiv > 12)) + printk(KERN_WARNING + "WM8976 N value outwith recommended range! N = %d\n",Ndiv); + + pll_div.n = Ndiv; + Nmod = target % source; + Kpart = FIXED_PLL_SIZE * (long long)Nmod; + + do_div(Kpart, source); + + K = Kpart & 0xFFFFFFFF; + + /* Check if we need to round */ + if ((K % 10) >= 5) + K += 5; + + /* Move down to proper range now rounding is done */ + K /= 10; + + pll_div.k = K; +} + +static int wm8976_set_dai_pll(struct snd_soc_dai *codec_dai, + int pll_id, unsigned int freq_in, unsigned int freq_out) +{ + struct snd_soc_codec *codec = codec_dai->codec; + u16 reg; + + if(freq_in == 0 || freq_out == 0) { + reg = wm8976_read_reg_cache(codec, WM8976_POWER1); + wm8976_write(codec, WM8976_POWER1, reg & 0x1df); + return 0; + } + + pll_factors(freq_out * 8, freq_in); + + wm8976_write(codec, WM8976_PLLN, (pll_div.pre << 4) | pll_div.n); + wm8976_write(codec, WM8976_PLLK1, pll_div.k >> 18); + wm8976_write(codec, WM8976_PLLK1, (pll_div.k >> 9) && 0x1ff); + wm8976_write(codec, WM8976_PLLK1, pll_div.k && 0x1ff); + reg = wm8976_read_reg_cache(codec, WM8976_POWER1); + wm8976_write(codec, WM8976_POWER1, reg | 0x020); + + + return 0; +} + +static int wm8976_set_dai_fmt(struct snd_soc_dai *codec_dai, + unsigned int fmt) +{ + struct snd_soc_codec *codec = codec_dai->codec; + u16 iface = wm8976_read_reg_cache(codec, WM8976_IFACE) & 0x3; + u16 clk = wm8976_read_reg_cache(codec, WM8976_CLOCK) & 0xfffe; + + /* set master/slave audio interface */ + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + clk |= 0x0001; + break; + case SND_SOC_DAIFMT_CBS_CFS: + break; + default: + return -EINVAL; + } + + /* interface format */ + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + iface |= 0x0010; + break; + case SND_SOC_DAIFMT_RIGHT_J: + break; + case SND_SOC_DAIFMT_LEFT_J: + iface |= 0x0008; + break; + case SND_SOC_DAIFMT_DSP_A: + iface |= 0x00018; + break; + default: + return -EINVAL; + } + + /* clock inversion */ + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + case SND_SOC_DAIFMT_IB_IF: + iface |= 0x0180; + break; + case SND_SOC_DAIFMT_IB_NF: + iface |= 0x0100; + break; + case SND_SOC_DAIFMT_NB_IF: + iface |= 0x0080; + break; + default: + return -EINVAL; + } + + wm8976_write(codec, WM8976_IFACE, iface); + wm8976_write(codec, WM8976_CLOCK, clk); + + return 0; +} + +static int wm8976_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->codec; + u16 iface = wm8976_read_reg_cache(codec, WM8976_IFACE) & 0xff9f; + u16 adn = wm8976_read_reg_cache(codec, WM8976_ADD) & 0x1f1; + + /* bit size */ + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + break; + case SNDRV_PCM_FORMAT_S20_3LE: + iface |= 0x0020; + break; + case SNDRV_PCM_FORMAT_S24_LE: + iface |= 0x0040; + break; + } + + /* filter coefficient */ + switch (params_rate(params)) { + case SNDRV_PCM_RATE_8000: + adn |= 0x5 << 1; + break; + case SNDRV_PCM_RATE_11025: + adn |= 0x4 << 1; + break; + case SNDRV_PCM_RATE_16000: + adn |= 0x3 << 1; + break; + case SNDRV_PCM_RATE_22050: + adn |= 0x2 << 1; + break; + case SNDRV_PCM_RATE_32000: + adn |= 0x1 << 1; + break; + } + + /* set iface */ + wm8976_write(codec, WM8976_IFACE, iface); + wm8976_write(codec, WM8976_ADD, adn); + return 0; +} + +static int wm8976_set_dai_clkdiv(struct snd_soc_dai *codec_dai, + int div_id, int div) +{ + struct snd_soc_codec *codec = codec_dai->codec; + u16 reg; + + switch (div_id) { + case WM8976_MCLKDIV: + reg = wm8976_read_reg_cache(codec, WM8976_CLOCK) & 0x11f; + wm8976_write(codec, WM8976_CLOCK, reg | div); + break; + case WM8976_BCLKDIV: + reg = wm8976_read_reg_cache(codec, WM8976_CLOCK) & 0x1c7; + wm8976_write(codec, WM8976_CLOCK, reg | div); + break; + case WM8976_OPCLKDIV: + reg = wm8976_read_reg_cache(codec, WM8976_GPIO) & 0x1cf; + wm8976_write(codec, WM8976_GPIO, reg | div); + break; + case WM8976_DACOSR: + reg = wm8976_read_reg_cache(codec, WM8976_DAC) & 0x1f7; + wm8976_write(codec, WM8976_DAC, reg | div); + break; + case WM8976_ADCOSR: + reg = wm8976_read_reg_cache(codec, WM8976_ADC) & 0x1f7; + wm8976_write(codec, WM8976_ADC, reg | div); + break; + case WM8976_MCLKSEL: + reg = wm8976_read_reg_cache(codec, WM8976_CLOCK) & 0x0ff; + wm8976_write(codec, WM8976_CLOCK, reg | div); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int wm8976_mute(struct snd_soc_dai *dai, int mute) +{ + struct snd_soc_codec *codec = dai->codec; + u16 mute_reg = wm8976_read_reg_cache(codec, WM8976_DAC) & 0xffbf; + + if(mute) + wm8976_write(codec, WM8976_DAC, mute_reg | 0x40); + else + wm8976_write(codec, WM8976_DAC, mute_reg); + + return 0; +} + +/* TODO: liam need to make this lower power with dapm */ +static int wm8976_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level) +{ + + switch (level) { + case SND_SOC_BIAS_ON: + wm8976_write(codec, WM8976_POWER1, 0x1ff); + wm8976_write(codec, WM8976_POWER2, 0x1ff); + wm8976_write(codec, WM8976_POWER3, 0x1ff); + break; + case SND_SOC_BIAS_STANDBY: + case SND_SOC_BIAS_PREPARE: + break; + case SND_SOC_BIAS_OFF: + wm8976_write(codec, WM8976_POWER1, 0x0); + wm8976_write(codec, WM8976_POWER2, 0x0); + wm8976_write(codec, WM8976_POWER3, 0x0); + break; + } + codec->bias_level = level; + return 0; +} + +#define WM8976_RATES \ + (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \ + SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ + SNDRV_PCM_RATE_48000) + +#define WM8976_FORMATS \ + (SNDRV_PCM_FORMAT_S16_LE | SNDRV_PCM_FORMAT_S20_3LE | \ + SNDRV_PCM_FORMAT_S24_3LE | SNDRV_PCM_FORMAT_S24_LE) + +struct snd_soc_dai wm8976_dai = { + .name = "WM8976 HiFi", + .playback = { + .stream_name = "Playback", + .channels_min = 1, + .channels_max = 2, + .rates = WM8976_RATES, + .formats = WM8976_FORMATS,}, + .capture = { + .stream_name = "Capture", + .channels_min = 1, + .channels_max = 1, + .rates = WM8976_RATES, + .formats = WM8976_FORMATS,}, + .ops = { + .hw_params = wm8976_hw_params, + .digital_mute = wm8976_mute, + .set_fmt = wm8976_set_dai_fmt, + .set_clkdiv = wm8976_set_dai_clkdiv, + .set_pll = wm8976_set_dai_pll, + }, +}; +EXPORT_SYMBOL_GPL(wm8976_dai); + +static int wm8976_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + + wm8976_set_bias_level(codec, SND_SOC_BIAS_OFF); + return 0; +} + +static int wm8976_resume(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + int i; + u8 data[2]; + u16 *cache = codec->reg_cache; + + /* Sync reg_cache with the hardware */ + for (i = 0; i < ARRAY_SIZE(wm8976_reg); i++) { + data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001); + data[1] = cache[i] & 0x00ff; + codec->hw_write(codec->control_data, data, 2); + } + wm8976_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + wm8976_set_bias_level(codec, codec->suspend_bias_level); + return 0; +} + +/* + * initialise the WM8976 driver + * register the mixer and dsp interfaces with the kernel + */ +static int wm8976_init(struct snd_soc_device* socdev) +{ + struct snd_soc_codec *codec = socdev->codec; + int ret = 0; + + codec->name = "WM8976"; + codec->owner = THIS_MODULE; + codec->read = wm8976_read_reg_cache; + codec->write = wm8976_write; + codec->set_bias_level = wm8976_set_bias_level; + codec->dai = &wm8976_dai; + codec->num_dai = 1; + codec->reg_cache_size = ARRAY_SIZE(wm8976_reg); + codec->reg_cache = kmemdup(wm8976_reg, sizeof(wm8976_reg), GFP_KERNEL); + + if (codec->reg_cache == NULL) + return -ENOMEM; + + wm8976_reset(codec); + + /* register pcms */ + ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); + if(ret < 0) { + printk(KERN_ERR "wm8976: failed to create pcms\n"); + goto pcm_err; + } + + /* power on device */ + wm8976_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + wm8976_add_controls(codec); + wm8976_add_widgets(codec); + ret = snd_soc_init_card(socdev); + if (ret < 0) { + printk(KERN_ERR "wm8976: failed to register card\n"); + goto card_err; + } + return ret; + +card_err: + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); +pcm_err: + kfree(codec->reg_cache); + return ret; +} + +static struct snd_soc_device *wm8976_socdev; + +#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE) + +/* + * WM8976 2 wire address is 0x1a + */ +#define I2C_DRIVERID_WM8976 0xfefe /* liam - need a proper id */ + +static unsigned short normal_i2c[] = { 0, I2C_CLIENT_END }; + +/* Magic definition of all other variables and things */ +I2C_CLIENT_INSMOD; + +static struct i2c_driver wm8976_i2c_driver; +static struct i2c_client client_template; + +/* If the i2c layer weren't so broken, we could pass this kind of data + around */ + +static int wm8976_codec_probe(struct i2c_adapter *adap, int addr, int kind) +{ + struct snd_soc_device *socdev = wm8976_socdev; + struct wm8976_setup_data *setup = socdev->codec_data; + struct snd_soc_codec *codec = socdev->codec; + struct i2c_client *i2c; + int ret; + + if (addr != setup->i2c_address) + return -ENODEV; + + client_template.adapter = adap; + client_template.addr = addr; + + i2c = kmemdup(&client_template, sizeof(client_template), GFP_KERNEL); + if (i2c == NULL){ + kfree(codec); + return -ENOMEM; + } + + i2c_set_clientdata(i2c, codec); + + codec->control_data = i2c; + + ret = i2c_attach_client(i2c); + if(ret < 0) { + pr_err("failed to attach codec at addr %x\n", addr); + goto err; + } + + ret = wm8976_init(socdev); + if(ret < 0) { + pr_err("failed to initialise WM8976\n"); + goto err; + } + return ret; + +err: + kfree(codec); + kfree(i2c); + return ret; + +} + +static int wm8976_i2c_detach(struct i2c_client *client) +{ + struct snd_soc_codec *codec = i2c_get_clientdata(client); + i2c_detach_client(client); + kfree(codec->reg_cache); + kfree(client); + return 0; +} + +static int wm8976_i2c_attach(struct i2c_adapter *adap) +{ + return i2c_probe(adap, &addr_data, wm8976_codec_probe); +} + +/* corgi i2c codec control layer */ +static struct i2c_driver wm8976_i2c_driver = { + .driver = { + .name = "WM8976 I2C Codec", + .owner = THIS_MODULE, + }, + .id = I2C_DRIVERID_WM8976, + .attach_adapter = wm8976_i2c_attach, + .detach_client = wm8976_i2c_detach, + .command = NULL, +}; + +static struct i2c_client client_template = { + .name = "WM8976", + .driver = &wm8976_i2c_driver, +}; +#endif + +static int wm8976_probe(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct wm8976_setup_data *setup; + struct snd_soc_codec *codec; + int ret = 0; + + pr_info("WM8976 Audio Codec %s", WM8976_VERSION); + + setup = socdev->codec_data; + codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); + if (codec == NULL) + return -ENOMEM; + + socdev->codec = codec; + mutex_init(&codec->mutex); + INIT_LIST_HEAD(&codec->dapm_widgets); + INIT_LIST_HEAD(&codec->dapm_paths); + + wm8976_socdev = socdev; +#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE) + if (setup->i2c_address) { + normal_i2c[0] = setup->i2c_address; + codec->hw_write = (hw_write_t)i2c_master_send; + ret = i2c_add_driver(&wm8976_i2c_driver); + if (ret != 0) + printk(KERN_ERR "can't add i2c driver"); + } +#else + /* Add other interfaces here */ +#endif + return ret; +} + +/* power down chip */ +static int wm8976_remove(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + + if (codec->control_data) + wm8976_set_bias_level(codec, SND_SOC_BIAS_OFF); + + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); +#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE) + i2c_del_driver(&wm8976_i2c_driver); +#endif + kfree(codec); + + return 0; +} + +struct snd_soc_codec_device soc_codec_dev_wm8976 = { + .probe = wm8976_probe, + .remove = wm8976_remove, + .suspend = wm8976_suspend, + .resume = wm8976_resume, +}; +EXPORT_SYMBOL_GPL(soc_codec_dev_wm8976); + +static int __init wm8976_modinit(void) +{ + return snd_soc_register_dai(&wm8976_dai); +} +module_init(wm8976_modinit); + +static void __exit wm8976_exit(void) +{ + snd_soc_unregister_dai(&wm8976_dai); +} +module_exit(wm8976_exit); + +MODULE_DESCRIPTION("ASoC WM8976 driver"); +MODULE_AUTHOR("Graeme Gregory"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/wm8976.h b/sound/soc/codecs/wm8976.h new file mode 100644 index 0000000..308537b --- /dev/null +++ b/sound/soc/codecs/wm8976.h @@ -0,0 +1,112 @@ +/* + * wm8976.h -- WM8976 Soc Audio driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _WM8976_H +#define _WM8976_H + +/* WM8976 register space */ + +#define WM8976_RESET 0x0 +#define WM8976_POWER1 0x1 +#define WM8976_POWER2 0x2 +#define WM8976_POWER3 0x3 +#define WM8976_IFACE 0x4 +#define WM8976_COMP 0x5 +#define WM8976_CLOCK 0x6 +#define WM8976_ADD 0x7 +#define WM8976_GPIO 0x8 +#define WM8976_JACK1 0x9 +#define WM8976_DAC 0xa +#define WM8976_DACVOLL 0xb +#define WM8976_DACVOLR 0xc +#define WM8976_JACK2 0xd +#define WM8976_ADC 0xe +#define WM8976_ADCVOL 0xf +#define WM8976_EQ1 0x12 +#define WM8976_EQ2 0x13 +#define WM8976_EQ3 0x14 +#define WM8976_EQ4 0x15 +#define WM8976_EQ5 0x16 +#define WM8976_DACLIM1 0x18 +#define WM8976_DACLIM2 0x19 +#define WM8976_NOTCH1 0x1b +#define WM8976_NOTCH2 0x1c +#define WM8976_NOTCH3 0x1d +#define WM8976_NOTCH4 0x1e +#define WM8976_ALC1 0x20 +#define WM8976_ALC2 0x21 +#define WM8976_ALC3 0x22 +#define WM8976_NGATE 0x23 +#define WM8976_PLLN 0x24 +#define WM8976_PLLK1 0x25 +#define WM8976_PLLK2 0x26 +#define WM8976_PLLK3 0x27 +#define WM8976_3D 0x29 +#define WM8976_BEEP 0x2b +#define WM8976_INPUT 0x2c +#define WM8976_INPPGA 0x2d +#define WM8976_ADCBOOST 0x2f +#define WM8976_OUTPUT 0x31 +#define WM8976_MIXL 0x32 +#define WM8976_MIXR 0x33 +#define WM8976_HPVOLL 0x34 +#define WM8976_HPVOLR 0x35 +#define WM8976_SPKVOLL 0x36 +#define WM8976_SPKVOLR 0x37 +#define WM8976_OUT3MIX 0x38 +#define WM8976_MONOMIX 0x39 + +#define WM8976_CACHEREGNUM 58 + +/* + * WM8976 Clock dividers + */ +#define WM8976_MCLKDIV 0 +#define WM8976_BCLKDIV 1 +#define WM8976_OPCLKDIV 2 +#define WM8976_DACOSR 3 +#define WM8976_ADCOSR 4 +#define WM8976_MCLKSEL 5 + +#define WM8976_MCLK_MCLK (0 << 8) +#define WM8976_MCLK_PLL (1 << 8) + +#define WM8976_MCLK_DIV_1 (0 << 5) +#define WM8976_MCLK_DIV_1_5 (1 << 5) +#define WM8976_MCLK_DIV_2 (2 << 5) +#define WM8976_MCLK_DIV_3 (3 << 5) +#define WM8976_MCLK_DIV_4 (4 << 5) +#define WM8976_MCLK_DIV_5_5 (5 << 5) +#define WM8976_MCLK_DIV_6 (6 << 5) + +#define WM8976_BCLK_DIV_1 (0 << 2) +#define WM8976_BCLK_DIV_2 (1 << 2) +#define WM8976_BCLK_DIV_4 (2 << 2) +#define WM8976_BCLK_DIV_8 (3 << 2) +#define WM8976_BCLK_DIV_16 (4 << 2) +#define WM8976_BCLK_DIV_32 (5 << 2) + +#define WM8976_DACOSR_64 (0 << 3) +#define WM8976_DACOSR_128 (1 << 3) + +#define WM8976_ADCOSR_64 (0 << 3) +#define WM8976_ADCOSR_128 (1 << 3) + +#define WM8976_OPCLK_DIV_1 (0 << 4) +#define WM8976_OPCLK_DIV_2 (1 << 4) +#define WM8976_OPCLK_DIV_3 (2 << 4) +#define WM8976_OPCLK_DIV_4 (3 << 4) + +struct wm8976_setup_data { + unsigned short i2c_address; +}; + +extern struct snd_soc_dai wm8976_dai; +extern struct snd_soc_codec_device soc_codec_dev_wm8976; + +#endif diff --git a/sound/soc/codecs/wm8978.c b/sound/soc/codecs/wm8978.c new file mode 100644 index 0000000..1615652 --- /dev/null +++ b/sound/soc/codecs/wm8978.c @@ -0,0 +1,888 @@ +/* + * wm8978.c -- WM8978 ALSA Soc Audio driver + * + * Copyright 2007 Wolfson Microelectronics PLC. + * + * Authors: Liam Girdwood + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "wm8978.h" + +#define AUDIO_NAME "wm8978" +#define WM8978_VERSION "0.1" + +struct snd_soc_codec_device soc_codec_dev_wm8978; + +/* + * wm8978 register cache + * We can't read the WM8978 register space when we are + * using 2 wire for device control, so we cache them instead. + */ +static const u16 wm8978_reg[WM8978_CACHEREGNUM] = { + 0x0000, 0x0000, 0x0000, 0x0000, + 0x0050, 0x0000, 0x0140, 0x0000, + 0x0000, 0x0000, 0x0000, 0x00ff, + 0x00ff, 0x0000, 0x0100, 0x00ff, + 0x00ff, 0x0000, 0x012c, 0x002c, + 0x002c, 0x002c, 0x002c, 0x0000, + 0x0032, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, + 0x0038, 0x000b, 0x0032, 0x0000, + 0x0008, 0x000c, 0x0093, 0x00e9, + 0x0000, 0x0000, 0x0000, 0x0000, + 0x0033, 0x0010, 0x0010, 0x0100, + 0x0100, 0x0002, 0x0001, 0x0001, + 0x0039, 0x0039, 0x0039, 0x0039, + 0x0001, 0x0001, +}; + +/* + * read wm8978 register cache + */ +static inline unsigned int wm8978_read_reg_cache(struct snd_soc_codec *codec, + unsigned int reg) +{ + u16 *cache = codec->reg_cache; + if (reg == WM8978_RESET) + return 0; + if (reg >= WM8978_CACHEREGNUM) + return -1; + return cache[reg]; +} + +/* + * write wm8978 register cache + */ +static inline void wm8978_write_reg_cache(struct snd_soc_codec *codec, + u16 reg, unsigned int value) +{ + u16 *cache = codec->reg_cache; + if (reg >= WM8978_CACHEREGNUM) + return; + cache[reg] = value; +} + +/* + * write to the WM8978 register space + */ +static int wm8978_write(struct snd_soc_codec *codec, unsigned int reg, + unsigned int value) +{ + u8 data[2]; + + /* data is + * D15..D9 WM8978 register offset + * D8...D0 register data + */ + data[0] = (reg << 1) | ((value >> 8) & 0x0001); + data[1] = value & 0x00ff; + + wm8978_write_reg_cache (codec, reg, value); + if (codec->hw_write(codec->control_data, data, 2) == 2) + return 0; + else + return -1; +} + +#define wm8978_reset(c) wm8978_write(c, WM8978_RESET, 0) + +static const char *wm8978_companding[] = {"Off", "NC", "u-law", "A-law" }; +static const char *wm8978_deemp[] = {"None", "32kHz", "44.1kHz", "48kHz" }; +static const char *wm8978_eqmode[] = {"Capture", "Playback" }; +static const char *wm8978_bw[] = {"Narrow", "Wide" }; +static const char *wm8978_eq1[] = {"80Hz", "105Hz", "135Hz", "175Hz" }; +static const char *wm8978_eq2[] = {"230Hz", "300Hz", "385Hz", "500Hz" }; +static const char *wm8978_eq3[] = {"650Hz", "850Hz", "1.1kHz", "1.4kHz" }; +static const char *wm8978_eq4[] = {"1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz" }; +static const char *wm8978_eq5[] = {"5.3kHz", "6.9kHz", "9kHz", "11.7kHz" }; +static const char *wm8978_alc[] = + {"ALC both on", "ALC left only", "ALC right only", "Limiter" }; + +static const struct soc_enum wm8978_enum[] = { + SOC_ENUM_SINGLE(WM8978_COMP, 1, 4, wm8978_companding), /* adc */ + SOC_ENUM_SINGLE(WM8978_COMP, 3, 4, wm8978_companding), /* dac */ + SOC_ENUM_SINGLE(WM8978_DAC, 4, 4, wm8978_deemp), + SOC_ENUM_SINGLE(WM8978_EQ1, 8, 2, wm8978_eqmode), + + SOC_ENUM_SINGLE(WM8978_EQ1, 5, 4, wm8978_eq1), + SOC_ENUM_SINGLE(WM8978_EQ2, 8, 2, wm8978_bw), + SOC_ENUM_SINGLE(WM8978_EQ2, 5, 4, wm8978_eq2), + SOC_ENUM_SINGLE(WM8978_EQ3, 8, 2, wm8978_bw), + + SOC_ENUM_SINGLE(WM8978_EQ3, 5, 4, wm8978_eq3), + SOC_ENUM_SINGLE(WM8978_EQ4, 8, 2, wm8978_bw), + SOC_ENUM_SINGLE(WM8978_EQ4, 5, 4, wm8978_eq4), + SOC_ENUM_SINGLE(WM8978_EQ5, 8, 2, wm8978_bw), + + SOC_ENUM_SINGLE(WM8978_EQ5, 5, 4, wm8978_eq5), + SOC_ENUM_SINGLE(WM8978_ALC3, 8, 2, wm8978_alc), +}; + +static const struct snd_kcontrol_new wm8978_snd_controls[] = { +SOC_SINGLE("Digital Loopback Switch", WM8978_COMP, 0, 1, 0), + +SOC_ENUM("ADC Companding", wm8978_enum[0]), +SOC_ENUM("DAC Companding", wm8978_enum[1]), + +SOC_SINGLE("Jack Detection Enable", WM8978_JACK1, 6, 1, 0), + +SOC_SINGLE("DAC Right Inversion Switch", WM8978_DAC, 1, 1, 0), +SOC_SINGLE("DAC Left Inversion Switch", WM8978_DAC, 0, 1, 0), + +SOC_SINGLE("Left Playback Volume", WM8978_DACVOLL, 0, 127, 0), +SOC_SINGLE("Right Playback Volume", WM8978_DACVOLR, 0, 127, 0), + +SOC_SINGLE("High Pass Filter Switch", WM8978_ADC, 8, 1, 0), +SOC_SINGLE("High Pass Filter Switch", WM8978_ADC, 8, 1, 0), +SOC_SINGLE("High Pass Cut Off", WM8978_ADC, 4, 7, 0), +SOC_SINGLE("Right ADC Inversion Switch", WM8978_ADC, 1, 1, 0), +SOC_SINGLE("Left ADC Inversion Switch", WM8978_ADC, 0, 1, 0), + +SOC_SINGLE("Left Capture Volume", WM8978_ADCVOLL, 0, 127, 0), +SOC_SINGLE("Right Capture Volume", WM8978_ADCVOLR, 0, 127, 0), + +SOC_ENUM("Equaliser Function", wm8978_enum[3]), +SOC_ENUM("EQ1 Cut Off", wm8978_enum[4]), +SOC_SINGLE("EQ1 Volume", WM8978_EQ1, 0, 31, 1), + +SOC_ENUM("Equaliser EQ2 Bandwith", wm8978_enum[5]), +SOC_ENUM("EQ2 Cut Off", wm8978_enum[6]), +SOC_SINGLE("EQ2 Volume", WM8978_EQ2, 0, 31, 1), + +SOC_ENUM("Equaliser EQ3 Bandwith", wm8978_enum[7]), +SOC_ENUM("EQ3 Cut Off", wm8978_enum[8]), +SOC_SINGLE("EQ3 Volume", WM8978_EQ3, 0, 31, 1), + +SOC_ENUM("Equaliser EQ4 Bandwith", wm8978_enum[9]), +SOC_ENUM("EQ4 Cut Off", wm8978_enum[10]), +SOC_SINGLE("EQ4 Volume", WM8978_EQ4, 0, 31, 1), + +SOC_ENUM("Equaliser EQ5 Bandwith", wm8978_enum[11]), +SOC_ENUM("EQ5 Cut Off", wm8978_enum[12]), +SOC_SINGLE("EQ5 Volume", WM8978_EQ5, 0, 31, 1), + +SOC_SINGLE("DAC Playback Limiter Switch", WM8978_DACLIM1, 8, 1, 0), +SOC_SINGLE("DAC Playback Limiter Decay", WM8978_DACLIM1, 4, 15, 0), +SOC_SINGLE("DAC Playback Limiter Attack", WM8978_DACLIM1, 0, 15, 0), + +SOC_SINGLE("DAC Playback Limiter Threshold", WM8978_DACLIM2, 4, 7, 0), +SOC_SINGLE("DAC Playback Limiter Boost", WM8978_DACLIM2, 0, 15, 0), + +SOC_SINGLE("ALC Enable Switch", WM8978_ALC1, 8, 1, 0), +SOC_SINGLE("ALC Capture Max Gain", WM8978_ALC1, 3, 7, 0), +SOC_SINGLE("ALC Capture Min Gain", WM8978_ALC1, 0, 7, 0), + +SOC_SINGLE("ALC Capture ZC Switch", WM8978_ALC2, 8, 1, 0), +SOC_SINGLE("ALC Capture Hold", WM8978_ALC2, 4, 7, 0), +SOC_SINGLE("ALC Capture Target", WM8978_ALC2, 0, 15, 0), + +SOC_ENUM("ALC Capture Mode", wm8978_enum[13]), +SOC_SINGLE("ALC Capture Decay", WM8978_ALC3, 4, 15, 0), +SOC_SINGLE("ALC Capture Attack", WM8978_ALC3, 0, 15, 0), + +SOC_SINGLE("ALC Capture Noise Gate Switch", WM8978_NGATE, 3, 1, 0), +SOC_SINGLE("ALC Capture Noise Gate Threshold", WM8978_NGATE, 0, 7, 0), + +SOC_SINGLE("Left Capture PGA ZC Switch", WM8978_INPPGAL, 7, 1, 0), +SOC_SINGLE("Left Capture PGA Volume", WM8978_INPPGAL, 0, 63, 0), + +SOC_SINGLE("Right Capture PGA ZC Switch", WM8978_INPPGAR, 7, 1, 0), +SOC_SINGLE("Right Capture PGA Volume", WM8978_INPPGAR, 0, 63, 0), + +SOC_SINGLE("Left Headphone Playback ZC Switch", WM8978_HPVOLL, 7, 1, 0), +SOC_SINGLE("Left Headphone Playback Switch", WM8978_HPVOLL, 6, 1, 1), +SOC_SINGLE("Left Headphone Playback Volume", WM8978_HPVOLL, 0, 63, 0), + +SOC_SINGLE("Right Headphone Playback ZC Switch", WM8978_HPVOLR, 7, 1, 0), +SOC_SINGLE("Right Headphone Playback Switch", WM8978_HPVOLR, 6, 1, 1), +SOC_SINGLE("Right Headphone Playback Volume", WM8978_HPVOLR, 0, 63, 0), + +SOC_SINGLE("Left Speaker Playback ZC Switch", WM8978_SPKVOLL, 7, 1, 0), +SOC_SINGLE("Left Speaker Playback Switch", WM8978_SPKVOLL, 6, 1, 1), +SOC_SINGLE("Left Speaker Playback Volume", WM8978_SPKVOLL, 0, 63, 0), + +SOC_SINGLE("Right Speaker Playback ZC Switch", WM8978_SPKVOLR, 7, 1, 0), +SOC_SINGLE("Right Speaker Playback Switch", WM8978_SPKVOLR, 6, 1, 1), +SOC_SINGLE("Right Speaker Playback Volume", WM8978_SPKVOLR, 0, 63, 0), + +SOC_DOUBLE_R("Capture Boost(+20dB)", WM8978_ADCBOOSTL, WM8978_ADCBOOSTR, + 8, 1, 0), +}; + +/* add non dapm controls */ +static int wm8978_add_controls(struct snd_soc_codec *codec) +{ + int err, i; + + for (i = 0; i < ARRAY_SIZE(wm8978_snd_controls); i++) { + err = snd_ctl_add(codec->card, + snd_soc_cnew(&wm8978_snd_controls[i],codec, NULL)); + if (err < 0) + return err; + } + + return 0; +} + +/* Left Output Mixer */ +static const struct snd_kcontrol_new wm8978_left_mixer_controls[] = { +SOC_DAPM_SINGLE("Right PCM Playback Switch", WM8978_OUTPUT, 6, 1, 1), +SOC_DAPM_SINGLE("Left PCM Playback Switch", WM8978_MIXL, 0, 1, 1), +SOC_DAPM_SINGLE("Line Bypass Switch", WM8978_MIXL, 1, 1, 0), +SOC_DAPM_SINGLE("Aux Playback Switch", WM8978_MIXL, 5, 1, 0), +}; + +/* Right Output Mixer */ +static const struct snd_kcontrol_new wm8978_right_mixer_controls[] = { +SOC_DAPM_SINGLE("Left PCM Playback Switch", WM8978_OUTPUT, 5, 1, 1), +SOC_DAPM_SINGLE("Right PCM Playback Switch", WM8978_MIXR, 0, 1, 1), +SOC_DAPM_SINGLE("Line Bypass Switch", WM8978_MIXR, 1, 1, 0), +SOC_DAPM_SINGLE("Aux Playback Switch", WM8978_MIXR, 5, 1, 0), +}; + +/* Left AUX Input boost vol */ +static const struct snd_kcontrol_new wm8978_laux_boost_controls = +SOC_DAPM_SINGLE("Left Aux Volume", WM8978_ADCBOOSTL, 0, 3, 0); + +/* Right AUX Input boost vol */ +static const struct snd_kcontrol_new wm8978_raux_boost_controls = +SOC_DAPM_SINGLE("Right Aux Volume", WM8978_ADCBOOSTR, 0, 3, 0); + +/* Left Input boost vol */ +static const struct snd_kcontrol_new wm8978_lmic_boost_controls = +SOC_DAPM_SINGLE("Left Input Volume", WM8978_ADCBOOSTL, 4, 3, 0); + +/* Right Input boost vol */ +static const struct snd_kcontrol_new wm8978_rmic_boost_controls = +SOC_DAPM_SINGLE("Right Input Volume", WM8978_ADCBOOSTR, 4, 3, 0); + +/* Left Aux In to PGA */ +static const struct snd_kcontrol_new wm8978_laux_capture_boost_controls = +SOC_DAPM_SINGLE("Left Capture Switch", WM8978_ADCBOOSTL, 8, 1, 0); + +/* Right Aux In to PGA */ +static const struct snd_kcontrol_new wm8978_raux_capture_boost_controls = +SOC_DAPM_SINGLE("Right Capture Switch", WM8978_ADCBOOSTR, 8, 1, 0); + +/* Left Input P In to PGA */ +static const struct snd_kcontrol_new wm8978_lmicp_capture_boost_controls = +SOC_DAPM_SINGLE("Left Input P Capture Boost Switch", WM8978_INPUT, 0, 1, 0); + +/* Right Input P In to PGA */ +static const struct snd_kcontrol_new wm8978_rmicp_capture_boost_controls = +SOC_DAPM_SINGLE("Right Input P Capture Boost Switch", WM8978_INPUT, 4, 1, 0); + +/* Left Input N In to PGA */ +static const struct snd_kcontrol_new wm8978_lmicn_capture_boost_controls = +SOC_DAPM_SINGLE("Left Input N Capture Boost Switch", WM8978_INPUT, 1, 1, 0); + +/* Right Input N In to PGA */ +static const struct snd_kcontrol_new wm8978_rmicn_capture_boost_controls = +SOC_DAPM_SINGLE("Right Input N Capture Boost Switch", WM8978_INPUT, 5, 1, 0); + +// TODO Widgets +static const struct snd_soc_dapm_widget wm8978_dapm_widgets[] = { +#if 0 +//SND_SOC_DAPM_MUTE("Mono Mute", WM8978_MONOMIX, 6, 0), +//SND_SOC_DAPM_MUTE("Speaker Mute", WM8978_SPKMIX, 6, 0), + +SND_SOC_DAPM_MIXER("Speaker Mixer", WM8978_POWER3, 2, 0, + &wm8978_speaker_mixer_controls[0], + ARRAY_SIZE(wm8978_speaker_mixer_controls)), +SND_SOC_DAPM_MIXER("Mono Mixer", WM8978_POWER3, 3, 0, + &wm8978_mono_mixer_controls[0], + ARRAY_SIZE(wm8978_mono_mixer_controls)), +SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM8978_POWER3, 0, 0), +SND_SOC_DAPM_ADC("ADC", "HiFi Capture", WM8978_POWER3, 0, 0), +SND_SOC_DAPM_PGA("Aux Input", WM8978_POWER1, 6, 0, NULL, 0), +SND_SOC_DAPM_PGA("SpkN Out", WM8978_POWER3, 5, 0, NULL, 0), +SND_SOC_DAPM_PGA("SpkP Out", WM8978_POWER3, 6, 0, NULL, 0), +SND_SOC_DAPM_PGA("Mono Out", WM8978_POWER3, 7, 0, NULL, 0), +SND_SOC_DAPM_PGA("Mic PGA", WM8978_POWER2, 2, 0, NULL, 0), + +SND_SOC_DAPM_PGA("Aux Boost", SND_SOC_NOPM, 0, 0, + &wm8978_aux_boost_controls, 1), +SND_SOC_DAPM_PGA("Mic Boost", SND_SOC_NOPM, 0, 0, + &wm8978_mic_boost_controls, 1), +SND_SOC_DAPM_SWITCH("Capture Boost", SND_SOC_NOPM, 0, 0, + &wm8978_capture_boost_controls), + +SND_SOC_DAPM_MIXER("Boost Mixer", WM8978_POWER2, 4, 0, NULL, 0), + +SND_SOC_DAPM_MICBIAS("Mic Bias", WM8978_POWER1, 4, 0), + +SND_SOC_DAPM_INPUT("MICN"), +SND_SOC_DAPM_INPUT("MICP"), +SND_SOC_DAPM_INPUT("AUX"), +SND_SOC_DAPM_OUTPUT("MONOOUT"), +SND_SOC_DAPM_OUTPUT("SPKOUTP"), +SND_SOC_DAPM_OUTPUT("SPKOUTN"), +#endif +}; + +static const struct snd_soc_dapm_route audio_map[] = { + /* Mono output mixer */ + {"Mono Mixer", "PCM Playback Switch", "DAC"}, + {"Mono Mixer", "Aux Playback Switch", "Aux Input"}, + {"Mono Mixer", "Line Bypass Switch", "Boost Mixer"}, + + /* Speaker output mixer */ + {"Speaker Mixer", "PCM Playback Switch", "DAC"}, + {"Speaker Mixer", "Aux Playback Switch", "Aux Input"}, + {"Speaker Mixer", "Line Bypass Switch", "Boost Mixer"}, + + /* Outputs */ + {"Mono Out", NULL, "Mono Mixer"}, + {"MONOOUT", NULL, "Mono Out"}, + {"SpkN Out", NULL, "Speaker Mixer"}, + {"SpkP Out", NULL, "Speaker Mixer"}, + {"SPKOUTN", NULL, "SpkN Out"}, + {"SPKOUTP", NULL, "SpkP Out"}, + + /* Boost Mixer */ + {"Boost Mixer", NULL, "ADC"}, + {"Capture Boost Switch", "Aux Capture Boost Switch", "AUX"}, + {"Aux Boost", "Aux Volume", "Boost Mixer"}, + {"Capture Boost", "Capture Switch", "Boost Mixer"}, + {"Mic Boost", "Mic Volume", "Boost Mixer"}, + + /* Inputs */ + {"MICP", NULL, "Mic Boost"}, + {"MICN", NULL, "Mic PGA"}, + {"Mic PGA", NULL, "Capture Boost"}, + {"AUX", NULL, "Aux Input"}, +}; + +static int wm8978_add_widgets(struct snd_soc_codec *codec) +{ + snd_soc_dapm_new_controls(codec, wm8978_dapm_widgets, + ARRAY_SIZE(wm8978_dapm_widgets)); + + snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + + snd_soc_dapm_new_widgets(codec); + return 0; +} + +struct pll_ { + unsigned int in_hz, out_hz; + unsigned int pre:4; /* prescale - 1 */ + unsigned int n:4; + unsigned int k; +}; + +static struct pll_ pll[] = { + {12000000, 11289600, 0, 7, 0x86c220}, + {12000000, 12288000, 0, 8, 0x3126e8}, + {13000000, 11289600, 0, 6, 0xf28bd4}, + {13000000, 12288000, 0, 7, 0x8fd525}, + {12288000, 11289600, 0, 7, 0x59999a}, + {11289600, 12288000, 0, 8, 0x80dee9}, + /* TODO: liam - add more entries */ +}; + +static int wm8978_set_dai_pll(struct snd_soc_dai *codec_dai, + int pll_id, unsigned int freq_in, unsigned int freq_out) +{ + struct snd_soc_codec *codec = codec_dai->codec; + int i; + u16 reg; + + if(freq_in == 0 || freq_out == 0) { + reg = wm8978_read_reg_cache(codec, WM8978_POWER1); + wm8978_write(codec, WM8978_POWER1, reg & 0x1df); + return 0; + } + + for(i = 0; i < ARRAY_SIZE(pll); i++) { + if (freq_in == pll[i].in_hz && freq_out == pll[i].out_hz) { + wm8978_write(codec, WM8978_PLLN, (pll[i].pre << 4) | pll[i].n); + wm8978_write(codec, WM8978_PLLK1, pll[i].k >> 18); + wm8978_write(codec, WM8978_PLLK1, (pll[i].k >> 9) && 0x1ff); + wm8978_write(codec, WM8978_PLLK1, pll[i].k && 0x1ff); + reg = wm8978_read_reg_cache(codec, WM8978_POWER1); + wm8978_write(codec, WM8978_POWER1, reg | 0x020); + return 0; + } + } + return -EINVAL; +} + +static int wm8978_set_dai_fmt(struct snd_soc_dai *codec_dai, + unsigned int fmt) +{ + struct snd_soc_codec *codec = codec_dai->codec; + u16 iface = wm8978_read_reg_cache(codec, WM8978_IFACE) & 0x3; + u16 clk = wm8978_read_reg_cache(codec, WM8978_CLOCK) & 0xfffe; + + /* set master/slave audio interface */ + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + clk |= 0x0001; + break; + case SND_SOC_DAIFMT_CBS_CFS: + break; + default: + return -EINVAL; + } + + /* interface format */ + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + iface |= 0x0010; + break; + case SND_SOC_DAIFMT_RIGHT_J: + break; + case SND_SOC_DAIFMT_LEFT_J: + iface |= 0x0008; + break; + case SND_SOC_DAIFMT_DSP_A: + iface |= 0x00018; + break; + default: + return -EINVAL; + } + + /* clock inversion */ + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + case SND_SOC_DAIFMT_IB_IF: + iface |= 0x0180; + break; + case SND_SOC_DAIFMT_IB_NF: + iface |= 0x0100; + break; + case SND_SOC_DAIFMT_NB_IF: + iface |= 0x0080; + break; + default: + return -EINVAL; + } + + wm8978_write(codec, WM8978_IFACE, iface); + return 0; +} + +static int wm8978_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->codec; + u16 iface = wm8978_read_reg_cache(codec, WM8978_IFACE) & 0xff9f; + u16 adn = wm8978_read_reg_cache(codec, WM8978_ADD) & 0x1f1; + + /* bit size */ + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + break; + case SNDRV_PCM_FORMAT_S20_3LE: + iface |= 0x0020; + break; + case SNDRV_PCM_FORMAT_S24_LE: + iface |= 0x0040; + break; + } + + /* filter coefficient */ + switch (params_rate(params)) { + case SNDRV_PCM_RATE_8000: + adn |= 0x5 << 1; + break; + case SNDRV_PCM_RATE_11025: + adn |= 0x4 << 1; + break; + case SNDRV_PCM_RATE_16000: + adn |= 0x3 << 1; + break; + case SNDRV_PCM_RATE_22050: + adn |= 0x2 << 1; + break; + case SNDRV_PCM_RATE_32000: + adn |= 0x1 << 1; + break; + } + + /* set iface */ + wm8978_write(codec, WM8978_IFACE, iface); + wm8978_write(codec, WM8978_ADD, adn); + return 0; +} + +static int wm8978_set_dai_clkdiv(struct snd_soc_dai *codec_dai, + int div_id, int div) +{ + struct snd_soc_codec *codec = codec_dai->codec; + u16 reg; + + switch (div_id) { + case WM8978_MCLKDIV: + reg = wm8978_read_reg_cache(codec, WM8978_CLOCK) & 0x11f; + wm8978_write(codec, WM8978_CLOCK, reg | div); + break; + case WM8978_BCLKDIV: + reg = wm8978_read_reg_cache(codec, WM8978_CLOCK) & 0x1c7; + wm8978_write(codec, WM8978_CLOCK, reg | div); + break; + case WM8978_OPCLKDIV: + reg = wm8978_read_reg_cache(codec, WM8978_GPIO) & 0x1cf; + wm8978_write(codec, WM8978_GPIO, reg | div); + break; + case WM8978_DACOSR: + reg = wm8978_read_reg_cache(codec, WM8978_DAC) & 0x1f7; + wm8978_write(codec, WM8978_DAC, reg | div); + break; + case WM8978_ADCOSR: + reg = wm8978_read_reg_cache(codec, WM8978_ADC) & 0x1f7; + wm8978_write(codec, WM8978_ADC, reg | div); + break; + case WM8978_MCLKSEL: + reg = wm8978_read_reg_cache(codec, WM8978_CLOCK) & 0x0ff; + wm8978_write(codec, WM8978_CLOCK, reg | div); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int wm8978_mute(struct snd_soc_dai *dai, int mute) +{ + struct snd_soc_codec *codec = dai->codec; + u16 mute_reg = wm8978_read_reg_cache(codec, WM8978_DAC) & 0xffbf; + + if(mute) + wm8978_write(codec, WM8978_DAC, mute_reg | 0x40); + else + wm8978_write(codec, WM8978_DAC, mute_reg); + + return 0; +} + +/* TODO: liam need to make this lower power with dapm */ +static int wm8978_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level) +{ + + switch (level) { + case SND_SOC_BIAS_ON: + wm8978_write(codec, WM8978_POWER1, 0x1ff); + wm8978_write(codec, WM8978_POWER2, 0x1ff); + wm8978_write(codec, WM8978_POWER3, 0x1ff); + break; + case SND_SOC_BIAS_PREPARE: + case SND_SOC_BIAS_STANDBY: + break; + case SND_SOC_BIAS_OFF: + wm8978_write(codec, WM8978_POWER1, 0x0); + wm8978_write(codec, WM8978_POWER2, 0x0); + wm8978_write(codec, WM8978_POWER3, 0x0); + break; + } + codec->bias_level = level; + return 0; +} + +#define WM8978_RATES SNDRV_PCM_RATE_8000_48000 + +#define WM8978_FORMATS \ + (SNDRV_PCM_FORMAT_S16_LE | SNDRV_PCM_FORMAT_S20_3LE | \ + SNDRV_PCM_FORMAT_S24_3LE | SNDRV_PCM_FORMAT_S24_LE) + +struct snd_soc_dai wm8978_dai = { + .name = "WM8978 HiFi", + .playback = { + .stream_name = "Playback", + .channels_min = 1, + .channels_max = 2, + .rates = WM8978_RATES, + .formats = WM8978_FORMATS,}, + .capture = { + .stream_name = "Capture", + .channels_min = 1, + .channels_max = 2, + .rates = WM8978_RATES, + .formats = WM8978_FORMATS,}, + .ops = { + .hw_params = wm8978_hw_params, + .digital_mute = wm8978_mute, + .set_fmt = wm8978_set_dai_fmt, + .set_clkdiv = wm8978_set_dai_clkdiv, + .set_pll = wm8978_set_dai_pll, + }, +}; +EXPORT_SYMBOL_GPL(wm8978_dai); + +static int wm8978_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + + wm8978_set_bias_level(codec, SND_SOC_BIAS_OFF); + return 0; +} + +static int wm8978_resume(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + int i; + u8 data[2]; + u16 *cache = codec->reg_cache; + + /* Sync reg_cache with the hardware */ + for (i = 0; i < ARRAY_SIZE(wm8978_reg); i++) { + data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001); + data[1] = cache[i] & 0x00ff; + codec->hw_write(codec->control_data, data, 2); + } + wm8978_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + wm8978_set_bias_level(codec, codec->suspend_bias_level); + return 0; +} + +/* + * initialise the WM8978 driver + * register the mixer and dsp interfaces with the kernel + */ +static int wm8978_init(struct snd_soc_device* socdev) +{ + struct snd_soc_codec *codec = socdev->codec; + int ret = 0; + + codec->name = "WM8978"; + codec->owner = THIS_MODULE; + codec->read = wm8978_read_reg_cache; + codec->write = wm8978_write; + codec->set_bias_level = wm8978_set_bias_level; + codec->dai = &wm8978_dai; + codec->num_dai = 1; + codec->reg_cache_size = ARRAY_SIZE(wm8978_reg); + codec->reg_cache = kmemdup(wm8978_reg, sizeof(wm8978_reg), GFP_KERNEL); + + if (codec->reg_cache == NULL) + return -ENOMEM; + + wm8978_reset(codec); + + /* register pcms */ + ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); + if(ret < 0) { + printk(KERN_ERR "wm8978: failed to create pcms\n"); + goto pcm_err; + } + + /* power on device */ + wm8978_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + wm8978_add_controls(codec); + wm8978_add_widgets(codec); + ret = snd_soc_init_card(socdev); + if (ret < 0) { + printk(KERN_ERR "wm8978: failed to register card\n"); + goto card_err; + } + return ret; + +card_err: + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); +pcm_err: + kfree(codec->reg_cache); + return ret; +} + +static struct snd_soc_device *wm8978_socdev; + +#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE) + +/* + * WM8978 2 wire address is 0x1a + */ +#define I2C_DRIVERID_WM8978 0xfefe /* liam - need a proper id */ + +static unsigned short normal_i2c[] = { 0, I2C_CLIENT_END }; + +/* Magic definition of all other variables and things */ +I2C_CLIENT_INSMOD; + +static struct i2c_driver wm8978_i2c_driver; +static struct i2c_client client_template; + +/* If the i2c layer weren't so broken, we could pass this kind of data + around */ + +static int wm8978_codec_probe(struct i2c_adapter *adap, int addr, int kind) +{ + struct snd_soc_device *socdev = wm8978_socdev; + struct wm8978_setup_data *setup = socdev->codec_data; + struct snd_soc_codec *codec = socdev->codec; + struct i2c_client *i2c; + int ret; + + if (addr != setup->i2c_address) + return -ENODEV; + + client_template.adapter = adap; + client_template.addr = addr; + + i2c = kmemdup(&client_template, sizeof(client_template), GFP_KERNEL); + if (i2c == NULL){ + kfree(codec); + return -ENOMEM; + } + + i2c_set_clientdata(i2c, codec); + + codec->control_data = i2c; + + ret = i2c_attach_client(i2c); + if (ret < 0) { + pr_err("failed to attach codec at addr %x\n", addr); + goto err; + } + + ret = wm8978_init(socdev); + if (ret < 0) { + pr_err("failed to initialise WM8978\n"); + goto err; + } + return ret; + +err: + kfree(codec); + kfree(i2c); + return ret; + +} + +static int wm8978_i2c_detach(struct i2c_client *client) +{ + struct snd_soc_codec *codec = i2c_get_clientdata(client); + i2c_detach_client(client); + kfree(codec->reg_cache); + kfree(client); + return 0; +} + +static int wm8978_i2c_attach(struct i2c_adapter *adap) +{ + return i2c_probe(adap, &addr_data, wm8978_codec_probe); +} + +/* corgi i2c codec control layer */ +static struct i2c_driver wm8978_i2c_driver = { + .driver = { + .name = "WM8978 I2C Codec", + .owner = THIS_MODULE, + }, + .id = I2C_DRIVERID_WM8978, + .attach_adapter = wm8978_i2c_attach, + .detach_client = wm8978_i2c_detach, + .command = NULL, +}; + +static struct i2c_client client_template = { + .name = "WM8978", + .driver = &wm8978_i2c_driver, +}; +#endif + +static int wm8978_probe(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct wm8978_setup_data *setup; + struct snd_soc_codec *codec; + int ret = 0; + + pr_info("WM8978 Audio Codec %s", WM8978_VERSION); + + setup = socdev->codec_data; + codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); + if (codec == NULL) + return -ENOMEM; + + socdev->codec = codec; + mutex_init(&codec->mutex); + INIT_LIST_HEAD(&codec->dapm_widgets); + INIT_LIST_HEAD(&codec->dapm_paths); + + wm8978_socdev = socdev; +#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE) + if (setup->i2c_address) { + normal_i2c[0] = setup->i2c_address; + codec->hw_write = (hw_write_t)i2c_master_send; + ret = i2c_add_driver(&wm8978_i2c_driver); + if (ret != 0) + printk(KERN_ERR "can't add i2c driver"); + } +#else + /* Add other interfaces here */ +#endif + return ret; +} + +/* power down chip */ +static int wm8978_remove(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + + if (codec->control_data) + wm8978_set_bias_level(codec, SND_SOC_BIAS_OFF); + + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); +#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE) + i2c_del_driver(&wm8978_i2c_driver); +#endif + kfree(codec); + + return 0; +} + +struct snd_soc_codec_device soc_codec_dev_wm8978 = { + .probe = wm8978_probe, + .remove = wm8978_remove, + .suspend = wm8978_suspend, + .resume = wm8978_resume, +}; +EXPORT_SYMBOL_GPL(soc_codec_dev_wm8978); + +static int __init wm8978_modinit(void) +{ + return snd_soc_register_dai(&wm8978_dai); +} +module_init(wm8978_modinit); + +static void __exit wm8978_exit(void) +{ + snd_soc_unregister_dai(&wm8978_dai); +} +module_exit(wm8978_exit); + +MODULE_DESCRIPTION("ASoC WM8978 driver"); +MODULE_AUTHOR("Liam Girdwood"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/wm8978.h b/sound/soc/codecs/wm8978.h new file mode 100644 index 0000000..84a9021 --- /dev/null +++ b/sound/soc/codecs/wm8978.h @@ -0,0 +1,116 @@ +/* + * wm8978.h -- WM8978 Soc Audio driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _WM8978_H +#define _WM8978_H + +/* WM8978 register space */ + +#define WM8978_RESET 0x0 +#define WM8978_POWER1 0x1 +#define WM8978_POWER2 0x2 +#define WM8978_POWER3 0x3 +#define WM8978_IFACE 0x4 +#define WM8978_COMP 0x5 +#define WM8978_CLOCK 0x6 +#define WM8978_ADD 0x7 +#define WM8978_GPIO 0x8 +#define WM8978_JACK1 0x9 +#define WM8978_DAC 0xa +#define WM8978_DACVOLL 0xb +#define WM8978_DACVOLR 0xc +#define WM8978_JACK2 0xd +#define WM8978_ADC 0xe +#define WM8978_ADCVOLL 0xf +#define WM8978_ADCVOLR 0x10 +#define WM8978_EQ1 0x12 +#define WM8978_EQ2 0x13 +#define WM8978_EQ3 0x14 +#define WM8978_EQ4 0x15 +#define WM8978_EQ5 0x16 +#define WM8978_DACLIM1 0x18 +#define WM8978_DACLIM2 0x19 +#define WM8978_NOTCH1 0x1b +#define WM8978_NOTCH2 0x1c +#define WM8978_NOTCH3 0x1d +#define WM8978_NOTCH4 0x1e +#define WM8978_ALC1 0x20 +#define WM8978_ALC2 0x21 +#define WM8978_ALC3 0x22 +#define WM8978_NGATE 0x23 +#define WM8978_PLLN 0x24 +#define WM8978_PLLK1 0x25 +#define WM8978_PLLK2 0x26 +#define WM8978_PLLK3 0x27 +#define WM8978_VIDEO 0x28 +#define WM8978_3D 0x29 +#define WM8978_BEEP 0x2b +#define WM8978_INPUT 0x2c +#define WM8978_INPPGAL 0x2d +#define WM8978_INPPGAR 0x2e +#define WM8978_ADCBOOSTL 0x2f +#define WM8978_ADCBOOSTR 0x30 +#define WM8978_OUTPUT 0x31 +#define WM8978_MIXL 0x32 +#define WM8978_MIXR 0x33 +#define WM8978_HPVOLL 0x34 +#define WM8978_HPVOLR 0x35 +#define WM8978_SPKVOLL 0x36 +#define WM8978_SPKVOLR 0x37 +#define WM8978_OUT3MIX 0x38 +#define WM8978_MONOMIX 0x39 + +#define WM8978_CACHEREGNUM 58 + +/* + * WM8978 Clock dividers + */ +#define WM8978_MCLKDIV 0 +#define WM8978_BCLKDIV 1 +#define WM8978_OPCLKDIV 2 +#define WM8978_DACOSR 3 +#define WM8978_ADCOSR 4 +#define WM8978_MCLKSEL 5 + +#define WM8978_MCLK_MCLK (0 << 8) +#define WM8978_MCLK_PLL (1 << 8) + +#define WM8978_MCLK_DIV_1 (0 << 5) +#define WM8978_MCLK_DIV_1_5 (1 << 5) +#define WM8978_MCLK_DIV_2 (2 << 5) +#define WM8978_MCLK_DIV_3 (3 << 5) +#define WM8978_MCLK_DIV_4 (4 << 5) +#define WM8978_MCLK_DIV_5_5 (5 << 5) +#define WM8978_MCLK_DIV_6 (6 << 5) + +#define WM8978_BCLK_DIV_1 (0 << 2) +#define WM8978_BCLK_DIV_2 (1 << 2) +#define WM8978_BCLK_DIV_4 (2 << 2) +#define WM8978_BCLK_DIV_8 (3 << 2) +#define WM8978_BCLK_DIV_16 (4 << 2) +#define WM8978_BCLK_DIV_32 (5 << 2) + +#define WM8978_DACOSR_64 (0 << 3) +#define WM8978_DACOSR_128 (1 << 3) + +#define WM8978_ADCOSR_64 (0 << 3) +#define WM8978_ADCOSR_128 (1 << 3) + +#define WM8978_OPCLK_DIV_1 (0 << 4) +#define WM8978_OPCLK_DIV_2 (1 << 4) +#define WM8978_OPCLK_DIV_3 (2 << 4) +#define WM8978_OPCLK_DIV_4 (3 << 4) + +struct wm8978_setup_data { + unsigned short i2c_address; +}; + +extern struct snd_soc_dai wm8978_dai; +extern struct snd_soc_codec_device soc_codec_dev_wm8978; + +#endif diff --git a/sound/soc/codecs/wm8980.c b/sound/soc/codecs/wm8980.c new file mode 100644 index 0000000..a076745 --- /dev/null +++ b/sound/soc/codecs/wm8980.c @@ -0,0 +1,890 @@ +/* + * wm8980.c -- WM8980 ALSA Soc Audio driver + * + * Copyright 2006 Wolfson Microelectronics PLC. + * + * Authors: + * Mike Arthur + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "wm8980.h" + +#define AUDIO_NAME "wm8980" +#define WM8980_VERSION "0.3" + +/* + * wm8980 register cache + * We can't read the WM8980 register space when we are + * using 2 wire for device control, so we cache them instead. + */ +static const u16 wm8980_reg[WM8980_CACHEREGNUM] = { + 0x0000, 0x0000, 0x0000, 0x0000, + 0x0050, 0x0000, 0x0140, 0x0000, + 0x0000, 0x0000, 0x0000, 0x00ff, + 0x00ff, 0x0000, 0x0100, 0x00ff, + 0x00ff, 0x0000, 0x012c, 0x002c, + 0x002c, 0x002c, 0x002c, 0x0000, + 0x0032, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, + 0x0038, 0x000b, 0x0032, 0x0000, + 0x0008, 0x000c, 0x0093, 0x00e9, + 0x0000, 0x0000, 0x0000, 0x0000, + 0x0033, 0x0010, 0x0010, 0x0100, + 0x0100, 0x0002, 0x0001, 0x0001, + 0x0039, 0x0039, 0x0039, 0x0039, + 0x0001, 0x0001, +}; + +/* + * read wm8980 register cache + */ +static inline unsigned int wm8980_read_reg_cache(struct snd_soc_codec *codec, + unsigned int reg) +{ + u16 *cache = codec->reg_cache; + if (reg == WM8980_RESET) + return 0; + if (reg >= WM8980_CACHEREGNUM) + return -1; + return cache[reg]; +} + +/* + * write wm8980 register cache + */ +static inline void wm8980_write_reg_cache(struct snd_soc_codec *codec, + u16 reg, unsigned int value) +{ + u16 *cache = codec->reg_cache; + if (reg >= WM8980_CACHEREGNUM) + return; + cache[reg] = value; +} + +/* + * write to the WM8980 register space + */ +static int wm8980_write(struct snd_soc_codec *codec, unsigned int reg, + unsigned int value) +{ + u8 data[2]; + + /* data is + * D15..D9 WM8980 register offset + * D8...D0 register data + */ + data[0] = (reg << 1) | ((value >> 8) & 0x0001); + data[1] = value & 0x00ff; + + wm8980_write_reg_cache (codec, reg, value); + if (codec->hw_write(codec->control_data, data, 2) == 2) + return 0; + else + return -1; +} + +#define wm8980_reset(c) wm8980_write(c, WM8980_RESET, 0) + +static const char *wm8980_companding[] = {"Off", "NC", "u-law", "A-law" }; +static const char *wm8980_deemp[] = {"None", "32kHz", "44.1kHz", "48kHz" }; +static const char *wm8980_eqmode[] = {"Capture", "Playback" }; +static const char *wm8980_bw[] = {"Narrow", "Wide" }; +static const char *wm8980_eq1[] = {"80Hz", "105Hz", "135Hz", "175Hz" }; +static const char *wm8980_eq2[] = {"230Hz", "300Hz", "385Hz", "500Hz" }; +static const char *wm8980_eq3[] = {"650Hz", "850Hz", "1.1kHz", "1.4kHz" }; +static const char *wm8980_eq4[] = {"1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz" }; +static const char *wm8980_eq5[] = {"5.3kHz", "6.9kHz", "9kHz", "11.7kHz" }; +static const char *wm8980_alc[] = + {"ALC both on", "ALC left only", "ALC right only", "Limiter" }; + +static const struct soc_enum wm8980_enum[] = { + SOC_ENUM_SINGLE(WM8980_COMP, 1, 4, wm8980_companding), /* adc */ + SOC_ENUM_SINGLE(WM8980_COMP, 3, 4, wm8980_companding), /* dac */ + SOC_ENUM_SINGLE(WM8980_DAC, 4, 4, wm8980_deemp), + SOC_ENUM_SINGLE(WM8980_EQ1, 8, 2, wm8980_eqmode), + + SOC_ENUM_SINGLE(WM8980_EQ1, 5, 4, wm8980_eq1), + SOC_ENUM_SINGLE(WM8980_EQ2, 8, 2, wm8980_bw), + SOC_ENUM_SINGLE(WM8980_EQ2, 5, 4, wm8980_eq2), + SOC_ENUM_SINGLE(WM8980_EQ3, 8, 2, wm8980_bw), + + SOC_ENUM_SINGLE(WM8980_EQ3, 5, 4, wm8980_eq3), + SOC_ENUM_SINGLE(WM8980_EQ4, 8, 2, wm8980_bw), + SOC_ENUM_SINGLE(WM8980_EQ4, 5, 4, wm8980_eq4), + SOC_ENUM_SINGLE(WM8980_EQ5, 8, 2, wm8980_bw), + + SOC_ENUM_SINGLE(WM8980_EQ5, 5, 4, wm8980_eq5), + SOC_ENUM_SINGLE(WM8980_ALC3, 8, 2, wm8980_alc), +}; + +static const struct snd_kcontrol_new wm8980_snd_controls[] = { +SOC_SINGLE("Digital Loopback Switch", WM8980_COMP, 0, 1, 0), + +SOC_ENUM("ADC Companding", wm8980_enum[0]), +SOC_ENUM("DAC Companding", wm8980_enum[1]), + +SOC_SINGLE("Jack Detection Enable", WM8980_JACK1, 6, 1, 0), + +SOC_SINGLE("DAC Right Inversion Switch", WM8980_DAC, 1, 1, 0), +SOC_SINGLE("DAC Left Inversion Switch", WM8980_DAC, 0, 1, 0), + +SOC_SINGLE("Left Playback Volume", WM8980_DACVOLL, 0, 127, 0), +SOC_SINGLE("Right Playback Volume", WM8980_DACVOLR, 0, 127, 0), + +SOC_SINGLE("High Pass Filter Switch", WM8980_ADC, 8, 1, 0), +SOC_SINGLE("High Pass Filter Switch", WM8980_ADC, 8, 1, 0), +SOC_SINGLE("High Pass Cut Off", WM8980_ADC, 4, 7, 0), +SOC_SINGLE("Right ADC Inversion Switch", WM8980_ADC, 1, 1, 0), +SOC_SINGLE("Left ADC Inversion Switch", WM8980_ADC, 0, 1, 0), + +SOC_SINGLE("Left Capture Volume", WM8980_ADCVOLL, 0, 127, 0), +SOC_SINGLE("Right Capture Volume", WM8980_ADCVOLR, 0, 127, 0), + +SOC_ENUM("Equaliser Function", wm8980_enum[3]), +SOC_ENUM("EQ1 Cut Off", wm8980_enum[4]), +SOC_SINGLE("EQ1 Volume", WM8980_EQ1, 0, 31, 1), + +SOC_ENUM("Equaliser EQ2 Bandwith", wm8980_enum[5]), +SOC_ENUM("EQ2 Cut Off", wm8980_enum[6]), +SOC_SINGLE("EQ2 Volume", WM8980_EQ2, 0, 31, 1), + +SOC_ENUM("Equaliser EQ3 Bandwith", wm8980_enum[7]), +SOC_ENUM("EQ3 Cut Off", wm8980_enum[8]), +SOC_SINGLE("EQ3 Volume", WM8980_EQ3, 0, 31, 1), + +SOC_ENUM("Equaliser EQ4 Bandwith", wm8980_enum[9]), +SOC_ENUM("EQ4 Cut Off", wm8980_enum[10]), +SOC_SINGLE("EQ4 Volume", WM8980_EQ4, 0, 31, 1), + +SOC_ENUM("Equaliser EQ5 Bandwith", wm8980_enum[11]), +SOC_ENUM("EQ5 Cut Off", wm8980_enum[12]), +SOC_SINGLE("EQ5 Volume", WM8980_EQ5, 0, 31, 1), + +SOC_SINGLE("DAC Playback Limiter Switch", WM8980_DACLIM1, 8, 1, 0), +SOC_SINGLE("DAC Playback Limiter Decay", WM8980_DACLIM1, 4, 15, 0), +SOC_SINGLE("DAC Playback Limiter Attack", WM8980_DACLIM1, 0, 15, 0), + +SOC_SINGLE("DAC Playback Limiter Threshold", WM8980_DACLIM2, 4, 7, 0), +SOC_SINGLE("DAC Playback Limiter Boost", WM8980_DACLIM2, 0, 15, 0), + +SOC_SINGLE("ALC Enable Switch", WM8980_ALC1, 8, 1, 0), +SOC_SINGLE("ALC Capture Max Gain", WM8980_ALC1, 3, 7, 0), +SOC_SINGLE("ALC Capture Min Gain", WM8980_ALC1, 0, 7, 0), + +SOC_SINGLE("ALC Capture ZC Switch", WM8980_ALC2, 8, 1, 0), +SOC_SINGLE("ALC Capture Hold", WM8980_ALC2, 4, 7, 0), +SOC_SINGLE("ALC Capture Target", WM8980_ALC2, 0, 15, 0), + +SOC_ENUM("ALC Capture Mode", wm8980_enum[13]), +SOC_SINGLE("ALC Capture Decay", WM8980_ALC3, 4, 15, 0), +SOC_SINGLE("ALC Capture Attack", WM8980_ALC3, 0, 15, 0), + +SOC_SINGLE("ALC Capture Noise Gate Switch", WM8980_NGATE, 3, 1, 0), +SOC_SINGLE("ALC Capture Noise Gate Threshold", WM8980_NGATE, 0, 7, 0), + +SOC_SINGLE("Left Capture PGA ZC Switch", WM8980_INPPGAL, 7, 1, 0), +SOC_SINGLE("Left Capture PGA Volume", WM8980_INPPGAL, 0, 63, 0), + +SOC_SINGLE("Right Capture PGA ZC Switch", WM8980_INPPGAR, 7, 1, 0), +SOC_SINGLE("Right Capture PGA Volume", WM8980_INPPGAR, 0, 63, 0), + +SOC_SINGLE("Left Headphone Playback ZC Switch", WM8980_HPVOLL, 7, 1, 0), +SOC_SINGLE("Left Headphone Playback Switch", WM8980_HPVOLL, 6, 1, 1), +SOC_SINGLE("Left Headphone Playback Volume", WM8980_HPVOLL, 0, 63, 0), + +SOC_SINGLE("Right Headphone Playback ZC Switch", WM8980_HPVOLR, 7, 1, 0), +SOC_SINGLE("Right Headphone Playback Switch", WM8980_HPVOLR, 6, 1, 1), +SOC_SINGLE("Right Headphone Playback Volume", WM8980_HPVOLR, 0, 63, 0), + +SOC_SINGLE("Left Speaker Playback ZC Switch", WM8980_SPKVOLL, 7, 1, 0), +SOC_SINGLE("Left Speaker Playback Switch", WM8980_SPKVOLL, 6, 1, 1), +SOC_SINGLE("Left Speaker Playback Volume", WM8980_SPKVOLL, 0, 63, 0), + +SOC_SINGLE("Right Speaker Playback ZC Switch", WM8980_SPKVOLR, 7, 1, 0), +SOC_SINGLE("Right Speaker Playback Switch", WM8980_SPKVOLR, 6, 1, 1), +SOC_SINGLE("Right Speaker Playback Volume", WM8980_SPKVOLR, 0, 63, 0), + +SOC_DOUBLE_R("Capture Boost(+20dB)", WM8980_ADCBOOSTL, WM8980_ADCBOOSTR, + 8, 1, 0), +}; + +/* add non dapm controls */ +static int wm8980_add_controls(struct snd_soc_codec *codec) +{ + int err, i; + + for (i = 0; i < ARRAY_SIZE(wm8980_snd_controls); i++) { + err = snd_ctl_add(codec->card, + snd_soc_cnew(&wm8980_snd_controls[i],codec, NULL)); + if (err < 0) + return err; + } + + return 0; +} + +/* Left Output Mixer */ +static const struct snd_kcontrol_new wm8980_left_mixer_controls[] = { +SOC_DAPM_SINGLE("Right PCM Playback Switch", WM8980_OUTPUT, 6, 1, 1), +SOC_DAPM_SINGLE("Left PCM Playback Switch", WM8980_MIXL, 0, 1, 1), +SOC_DAPM_SINGLE("Line Bypass Switch", WM8980_MIXL, 1, 1, 0), +SOC_DAPM_SINGLE("Aux Playback Switch", WM8980_MIXL, 5, 1, 0), +}; + +/* Right Output Mixer */ +static const struct snd_kcontrol_new wm8980_right_mixer_controls[] = { +SOC_DAPM_SINGLE("Left PCM Playback Switch", WM8980_OUTPUT, 5, 1, 1), +SOC_DAPM_SINGLE("Right PCM Playback Switch", WM8980_MIXR, 0, 1, 1), +SOC_DAPM_SINGLE("Line Bypass Switch", WM8980_MIXR, 1, 1, 0), +SOC_DAPM_SINGLE("Aux Playback Switch", WM8980_MIXR, 5, 1, 0), +}; + +/* Left AUX Input boost vol */ +static const struct snd_kcontrol_new wm8980_laux_boost_controls = +SOC_DAPM_SINGLE("Left Aux Volume", WM8980_ADCBOOSTL, 0, 3, 0); + +/* Right AUX Input boost vol */ +static const struct snd_kcontrol_new wm8980_raux_boost_controls = +SOC_DAPM_SINGLE("Right Aux Volume", WM8980_ADCBOOSTR, 0, 3, 0); + +/* Left Input boost vol */ +static const struct snd_kcontrol_new wm8980_lmic_boost_controls = +SOC_DAPM_SINGLE("Left Input Volume", WM8980_ADCBOOSTL, 4, 3, 0); + +/* Right Input boost vol */ +static const struct snd_kcontrol_new wm8980_rmic_boost_controls = +SOC_DAPM_SINGLE("Right Input Volume", WM8980_ADCBOOSTR, 4, 3, 0); + +/* Left Aux In to PGA */ +static const struct snd_kcontrol_new wm8980_laux_capture_boost_controls = +SOC_DAPM_SINGLE("Left Capture Switch", WM8980_ADCBOOSTL, 8, 1, 0); + +/* Right Aux In to PGA */ +static const struct snd_kcontrol_new wm8980_raux_capture_boost_controls = +SOC_DAPM_SINGLE("Right Capture Switch", WM8980_ADCBOOSTR, 8, 1, 0); + +/* Left Input P In to PGA */ +static const struct snd_kcontrol_new wm8980_lmicp_capture_boost_controls = +SOC_DAPM_SINGLE("Left Input P Capture Boost Switch", WM8980_INPUT, 0, 1, 0); + +/* Right Input P In to PGA */ +static const struct snd_kcontrol_new wm8980_rmicp_capture_boost_controls = +SOC_DAPM_SINGLE("Right Input P Capture Boost Switch", WM8980_INPUT, 4, 1, 0); + +/* Left Input N In to PGA */ +static const struct snd_kcontrol_new wm8980_lmicn_capture_boost_controls = +SOC_DAPM_SINGLE("Left Input N Capture Boost Switch", WM8980_INPUT, 1, 1, 0); + +/* Right Input N In to PGA */ +static const struct snd_kcontrol_new wm8980_rmicn_capture_boost_controls = +SOC_DAPM_SINGLE("Right Input N Capture Boost Switch", WM8980_INPUT, 5, 1, 0); + +// TODO Widgets +static const struct snd_soc_dapm_widget wm8980_dapm_widgets[] = { +#if 0 +//SND_SOC_DAPM_MUTE("Mono Mute", WM8980_MONOMIX, 6, 0), +//SND_SOC_DAPM_MUTE("Speaker Mute", WM8980_SPKMIX, 6, 0), + +SND_SOC_DAPM_MIXER("Speaker Mixer", WM8980_POWER3, 2, 0, + &wm8980_speaker_mixer_controls[0], + ARRAY_SIZE(wm8980_speaker_mixer_controls)), +SND_SOC_DAPM_MIXER("Mono Mixer", WM8980_POWER3, 3, 0, + &wm8980_mono_mixer_controls[0], + ARRAY_SIZE(wm8980_mono_mixer_controls)), +SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM8980_POWER3, 0, 0), +SND_SOC_DAPM_ADC("ADC", "HiFi Capture", WM8980_POWER3, 0, 0), +SND_SOC_DAPM_PGA("Aux Input", WM8980_POWER1, 6, 0, NULL, 0), +SND_SOC_DAPM_PGA("SpkN Out", WM8980_POWER3, 5, 0, NULL, 0), +SND_SOC_DAPM_PGA("SpkP Out", WM8980_POWER3, 6, 0, NULL, 0), +SND_SOC_DAPM_PGA("Mono Out", WM8980_POWER3, 7, 0, NULL, 0), +SND_SOC_DAPM_PGA("Mic PGA", WM8980_POWER2, 2, 0, NULL, 0), + +SND_SOC_DAPM_PGA("Aux Boost", SND_SOC_NOPM, 0, 0, + &wm8980_aux_boost_controls, 1), +SND_SOC_DAPM_PGA("Mic Boost", SND_SOC_NOPM, 0, 0, + &wm8980_mic_boost_controls, 1), +SND_SOC_DAPM_SWITCH("Capture Boost", SND_SOC_NOPM, 0, 0, + &wm8980_capture_boost_controls), + +SND_SOC_DAPM_MIXER("Boost Mixer", WM8980_POWER2, 4, 0, NULL, 0), + +SND_SOC_DAPM_MICBIAS("Mic Bias", WM8980_POWER1, 4, 0), + +SND_SOC_DAPM_INPUT("MICN"), +SND_SOC_DAPM_INPUT("MICP"), +SND_SOC_DAPM_INPUT("AUX"), +SND_SOC_DAPM_OUTPUT("MONOOUT"), +SND_SOC_DAPM_OUTPUT("SPKOUTP"), +SND_SOC_DAPM_OUTPUT("SPKOUTN"), +#endif +}; + +static const struct snd_soc_dapm_route audio_map[] = { + /* Mono output mixer */ + {"Mono Mixer", "PCM Playback Switch", "DAC"}, + {"Mono Mixer", "Aux Playback Switch", "Aux Input"}, + {"Mono Mixer", "Line Bypass Switch", "Boost Mixer"}, + + /* Speaker output mixer */ + {"Speaker Mixer", "PCM Playback Switch", "DAC"}, + {"Speaker Mixer", "Aux Playback Switch", "Aux Input"}, + {"Speaker Mixer", "Line Bypass Switch", "Boost Mixer"}, + + /* Outputs */ + {"Mono Out", NULL, "Mono Mixer"}, + {"MONOOUT", NULL, "Mono Out"}, + {"SpkN Out", NULL, "Speaker Mixer"}, + {"SpkP Out", NULL, "Speaker Mixer"}, + {"SPKOUTN", NULL, "SpkN Out"}, + {"SPKOUTP", NULL, "SpkP Out"}, + + /* Boost Mixer */ + {"Boost Mixer", NULL, "ADC"}, + {"Capture Boost Switch", "Aux Capture Boost Switch", "AUX"}, + {"Aux Boost", "Aux Volume", "Boost Mixer"}, + {"Capture Boost", "Capture Switch", "Boost Mixer"}, + {"Mic Boost", "Mic Volume", "Boost Mixer"}, + + /* Inputs */ + {"MICP", NULL, "Mic Boost"}, + {"MICN", NULL, "Mic PGA"}, + {"Mic PGA", NULL, "Capture Boost"}, + {"AUX", NULL, "Aux Input"}, +}; + +static int wm8980_add_widgets(struct snd_soc_codec *codec) +{ + snd_soc_dapm_new_controls(codec, wm8980_dapm_widgets, + ARRAY_SIZE(wm8980_dapm_widgets)); + + snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + + snd_soc_dapm_new_widgets(codec); + return 0; +} + +struct pll_ { + unsigned int in_hz, out_hz; + unsigned int pre:4; /* prescale - 1 */ + unsigned int n:4; + unsigned int k; +}; + +static struct pll_ pll[] = { + {12000000, 11289600, 0, 7, 0x86c220}, + {12000000, 12288000, 0, 8, 0x3126e8}, + {13000000, 11289600, 0, 6, 0xf28bd4}, + {13000000, 12288000, 0, 7, 0x8fd525}, + {12288000, 11289600, 0, 7, 0x59999a}, + {11289600, 12288000, 0, 8, 0x80dee9}, + /* TODO: liam - add more entries */ +}; + +static int wm8980_set_dai_pll(struct snd_soc_dai *codec_dai, + int pll_id, unsigned int freq_in, unsigned int freq_out) +{ + struct snd_soc_codec *codec = codec_dai->codec; + int i; + u16 reg; + + if(freq_in == 0 || freq_out == 0) { + reg = wm8980_read_reg_cache(codec, WM8980_POWER1); + wm8980_write(codec, WM8980_POWER1, reg & 0x1df); + return 0; + } + + for(i = 0; i < ARRAY_SIZE(pll); i++) { + if (freq_in == pll[i].in_hz && freq_out == pll[i].out_hz) { + wm8980_write(codec, WM8980_PLLN, (pll[i].pre << 4) | pll[i].n); + wm8980_write(codec, WM8980_PLLK1, pll[i].k >> 18); + wm8980_write(codec, WM8980_PLLK1, (pll[i].k >> 9) && 0x1ff); + wm8980_write(codec, WM8980_PLLK1, pll[i].k && 0x1ff); + reg = wm8980_read_reg_cache(codec, WM8980_POWER1); + wm8980_write(codec, WM8980_POWER1, reg | 0x020); + return 0; + } + } + return -EINVAL; +} + +static int wm8980_set_dai_fmt(struct snd_soc_dai *codec_dai, + unsigned int fmt) +{ + struct snd_soc_codec *codec = codec_dai->codec; + u16 iface = wm8980_read_reg_cache(codec, WM8980_IFACE) & 0x3; + u16 clk = wm8980_read_reg_cache(codec, WM8980_CLOCK) & 0xfffe; + + /* set master/slave audio interface */ + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + clk |= 0x0001; + break; + case SND_SOC_DAIFMT_CBS_CFS: + break; + default: + return -EINVAL; + } + + /* interface format */ + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + iface |= 0x0010; + break; + case SND_SOC_DAIFMT_RIGHT_J: + break; + case SND_SOC_DAIFMT_LEFT_J: + iface |= 0x0008; + break; + case SND_SOC_DAIFMT_DSP_A: + iface |= 0x00018; + break; + default: + return -EINVAL; + } + + /* clock inversion */ + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + case SND_SOC_DAIFMT_IB_IF: + iface |= 0x0180; + break; + case SND_SOC_DAIFMT_IB_NF: + iface |= 0x0100; + break; + case SND_SOC_DAIFMT_NB_IF: + iface |= 0x0080; + break; + default: + return -EINVAL; + } + + wm8980_write(codec, WM8980_IFACE, iface); + return 0; +} + +static int wm8980_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->codec; + u16 iface = wm8980_read_reg_cache(codec, WM8980_IFACE) & 0xff9f; + u16 adn = wm8980_read_reg_cache(codec, WM8980_ADD) & 0x1f1; + + /* bit size */ + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + break; + case SNDRV_PCM_FORMAT_S20_3LE: + iface |= 0x0020; + break; + case SNDRV_PCM_FORMAT_S24_LE: + iface |= 0x0040; + break; + } + + /* filter coefficient */ + switch (params_rate(params)) { + case SNDRV_PCM_RATE_8000: + adn |= 0x5 << 1; + break; + case SNDRV_PCM_RATE_11025: + adn |= 0x4 << 1; + break; + case SNDRV_PCM_RATE_16000: + adn |= 0x3 << 1; + break; + case SNDRV_PCM_RATE_22050: + adn |= 0x2 << 1; + break; + case SNDRV_PCM_RATE_32000: + adn |= 0x1 << 1; + break; + } + + /* set iface */ + wm8980_write(codec, WM8980_IFACE, iface); + wm8980_write(codec, WM8980_ADD, adn); + return 0; +} + +static int wm8980_set_dai_clkdiv(struct snd_soc_dai *codec_dai, + int div_id, int div) +{ + struct snd_soc_codec *codec = codec_dai->codec; + u16 reg; + + switch (div_id) { + case WM8980_MCLKDIV: + reg = wm8980_read_reg_cache(codec, WM8980_CLOCK) & 0x11f; + wm8980_write(codec, WM8980_CLOCK, reg | div); + break; + case WM8980_BCLKDIV: + reg = wm8980_read_reg_cache(codec, WM8980_CLOCK) & 0x1c7; + wm8980_write(codec, WM8980_CLOCK, reg | div); + break; + case WM8980_OPCLKDIV: + reg = wm8980_read_reg_cache(codec, WM8980_GPIO) & 0x1cf; + wm8980_write(codec, WM8980_GPIO, reg | div); + break; + case WM8980_DACOSR: + reg = wm8980_read_reg_cache(codec, WM8980_DAC) & 0x1f7; + wm8980_write(codec, WM8980_DAC, reg | div); + break; + case WM8980_ADCOSR: + reg = wm8980_read_reg_cache(codec, WM8980_ADC) & 0x1f7; + wm8980_write(codec, WM8980_ADC, reg | div); + break; + case WM8980_MCLKSEL: + reg = wm8980_read_reg_cache(codec, WM8980_CLOCK) & 0x0ff; + wm8980_write(codec, WM8980_CLOCK, reg | div); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int wm8980_mute(struct snd_soc_dai *dai, int mute) +{ + struct snd_soc_codec *codec = dai->codec; + u16 mute_reg = wm8980_read_reg_cache(codec, WM8980_DAC) & 0xffbf; + + if(mute) + wm8980_write(codec, WM8980_DAC, mute_reg | 0x40); + else + wm8980_write(codec, WM8980_DAC, mute_reg); + + return 0; +} + +/* TODO: liam need to make this lower power with dapm */ +static int wm8980_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level) +{ + + switch (level) { + case SND_SOC_BIAS_ON: + wm8980_write(codec, WM8980_POWER1, 0x1ff); + wm8980_write(codec, WM8980_POWER2, 0x1ff); + wm8980_write(codec, WM8980_POWER3, 0x1ff); + break; + case SND_SOC_BIAS_PREPARE: + case SND_SOC_BIAS_STANDBY: + break; + case SND_SOC_BIAS_OFF: + wm8980_write(codec, WM8980_POWER1, 0x0); + wm8980_write(codec, WM8980_POWER2, 0x0); + wm8980_write(codec, WM8980_POWER3, 0x0); + break; + } + codec->bias_level = level; + return 0; +} + +#define WM8980_RATES \ + (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \ + SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ + SNDRV_PCM_RATE_48000) + +#define WM8980_FORMATS \ + (SNDRV_PCM_FORMAT_S16_LE | SNDRV_PCM_FORMAT_S20_3LE | \ + SNDRV_PCM_FORMAT_S24_3LE | SNDRV_PCM_FORMAT_S24_LE) + +struct snd_soc_dai wm8980_dai = { + .name = "WM8980 HiFi", + .playback = { + .stream_name = "Playback", + .channels_min = 1, + .channels_max = 2, + .rates = WM8980_RATES, + .formats = WM8980_FORMATS,}, + .capture = { + .stream_name = "Capture", + .channels_min = 1, + .channels_max = 2, + .rates = WM8980_RATES, + .formats = WM8980_FORMATS,}, + .ops = { + .hw_params = wm8980_hw_params, + .digital_mute = wm8980_mute, + .set_fmt = wm8980_set_dai_fmt, + .set_clkdiv = wm8980_set_dai_clkdiv, + .set_pll = wm8980_set_dai_pll, + }, +}; +EXPORT_SYMBOL_GPL(wm8980_dai); + +static int wm8980_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + + wm8980_set_bias_level(codec, SND_SOC_BIAS_OFF); + return 0; +} + +static int wm8980_resume(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + int i; + u8 data[2]; + u16 *cache = codec->reg_cache; + + /* Sync reg_cache with the hardware */ + for (i = 0; i < ARRAY_SIZE(wm8980_reg); i++) { + data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001); + data[1] = cache[i] & 0x00ff; + codec->hw_write(codec->control_data, data, 2); + } + wm8980_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + wm8980_set_bias_level(codec, codec->suspend_bias_level); + return 0; +} + +/* + * initialise the WM8980 driver + * register the mixer and dsp interfaces with the kernel + */ +static int wm8980_init(struct snd_soc_device* socdev) +{ + struct snd_soc_codec *codec = socdev->codec; + int ret = 0; + + codec->name = "WM8980"; + codec->owner = THIS_MODULE; + codec->read = wm8980_read_reg_cache; + codec->write = wm8980_write; + codec->set_bias_level = wm8980_set_bias_level; + codec->dai = &wm8980_dai; + codec->num_dai = 1; + codec->reg_cache_size = ARRAY_SIZE(wm8980_reg); + codec->reg_cache = kmemdup(wm8980_reg, sizeof(wm8980_reg), GFP_KERNEL); + + if (codec->reg_cache == NULL) + return -ENOMEM; + + wm8980_reset(codec); + + /* register pcms */ + ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); + if(ret < 0) { + printk(KERN_ERR "wm8980: failed to create pcms\n"); + goto pcm_err; + } + + /* power on device */ + wm8980_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + wm8980_add_controls(codec); + wm8980_add_widgets(codec); + ret = snd_soc_init_card(socdev); + if (ret < 0) { + printk(KERN_ERR "wm8980: failed to register card\n"); + goto card_err; + } + return ret; + +card_err: + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); +pcm_err: + kfree(codec->reg_cache); + return ret; +} + +static struct snd_soc_device *wm8980_socdev; + +#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE) + +/* + * WM8980 2 wire address is 0x1a + */ +#define I2C_DRIVERID_WM8980 0xfefe /* liam - need a proper id */ + +static unsigned short normal_i2c[] = { 0, I2C_CLIENT_END }; + +/* Magic definition of all other variables and things */ +I2C_CLIENT_INSMOD; + +static struct i2c_driver wm8980_i2c_driver; +static struct i2c_client client_template; + +/* If the i2c layer weren't so broken, we could pass this kind of data + around */ + +static int wm8980_codec_probe(struct i2c_adapter *adap, int addr, int kind) +{ + struct snd_soc_device *socdev = wm8980_socdev; + struct wm8980_setup_data *setup = socdev->codec_data; + struct snd_soc_codec *codec = socdev->codec; + struct i2c_client *i2c; + int ret; + + if (addr != setup->i2c_address) + return -ENODEV; + + client_template.adapter = adap; + client_template.addr = addr; + + i2c = kmemdup(&client_template, sizeof(client_template), GFP_KERNEL); + if (i2c == NULL){ + kfree(codec); + return -ENOMEM; + } + + i2c_set_clientdata(i2c, codec); + + codec->control_data = i2c; + + ret = i2c_attach_client(i2c); + if(ret < 0) { + pr_err("failed to attach codec at addr %x\n", addr); + goto err; + } + + ret = wm8980_init(socdev); + if(ret < 0) { + pr_err("failed to initialise WM8980\n"); + goto err; + } + return ret; + +err: + kfree(codec); + kfree(i2c); + return ret; + +} + +static int wm8980_i2c_detach(struct i2c_client *client) +{ + struct snd_soc_codec *codec = i2c_get_clientdata(client); + i2c_detach_client(client); + kfree(codec->reg_cache); + kfree(client); + return 0; +} + +static int wm8980_i2c_attach(struct i2c_adapter *adap) +{ + return i2c_probe(adap, &addr_data, wm8980_codec_probe); +} + +/* corgi i2c codec control layer */ +static struct i2c_driver wm8980_i2c_driver = { + .driver = { + .name = "WM8980 I2C Codec", + .owner = THIS_MODULE, + }, + .id = I2C_DRIVERID_WM8980, + .attach_adapter = wm8980_i2c_attach, + .detach_client = wm8980_i2c_detach, + .command = NULL, +}; + +static struct i2c_client client_template = { + .name = "WM8980", + .driver = &wm8980_i2c_driver, +}; +#endif + +static int wm8980_probe(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct wm8980_setup_data *setup; + struct snd_soc_codec *codec; + int ret = 0; + + pr_info("WM8980 Audio Codec %s", WM8980_VERSION); + + setup = socdev->codec_data; + codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); + if (codec == NULL) + return -ENOMEM; + + socdev->codec = codec; + mutex_init(&codec->mutex); + INIT_LIST_HEAD(&codec->dapm_widgets); + INIT_LIST_HEAD(&codec->dapm_paths); + + wm8980_socdev = socdev; +#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE) + if (setup->i2c_address) { + normal_i2c[0] = setup->i2c_address; + codec->hw_write = (hw_write_t)i2c_master_send; + ret = i2c_add_driver(&wm8980_i2c_driver); + if (ret != 0) + printk(KERN_ERR "can't add i2c driver"); + } +#else + /* Add other interfaces here */ +#endif + return ret; +} + +/* power down chip */ +static int wm8980_remove(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + + if (codec->control_data) + wm8980_set_bias_level(codec, SND_SOC_BIAS_OFF); + + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); +#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE) + i2c_del_driver(&wm8980_i2c_driver); +#endif + kfree(codec); + + return 0; +} + +struct snd_soc_codec_device soc_codec_dev_wm8980 = { + .probe = wm8980_probe, + .remove = wm8980_remove, + .suspend = wm8980_suspend, + .resume = wm8980_resume, +}; +EXPORT_SYMBOL_GPL(soc_codec_dev_wm8980); + +static int __init wm8980_modinit(void) +{ + return snd_soc_register_dai(&wm8980_dai); +} +module_init(wm8980_modinit); + +static void __exit wm8980_exit(void) +{ + snd_soc_unregister_dai(&wm8980_dai); +} +module_exit(wm8980_exit); + +MODULE_DESCRIPTION("ASoC WM8980 driver"); +MODULE_AUTHOR("Mike Arthur"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/wm8980.h b/sound/soc/codecs/wm8980.h new file mode 100644 index 0000000..8f8a824 --- /dev/null +++ b/sound/soc/codecs/wm8980.h @@ -0,0 +1,116 @@ +/* + * wm8980.h -- WM8980 Soc Audio driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _WM8980_H +#define _WM8980_H + +/* WM8980 register space */ + +#define WM8980_RESET 0x0 +#define WM8980_POWER1 0x1 +#define WM8980_POWER2 0x2 +#define WM8980_POWER3 0x3 +#define WM8980_IFACE 0x4 +#define WM8980_COMP 0x5 +#define WM8980_CLOCK 0x6 +#define WM8980_ADD 0x7 +#define WM8980_GPIO 0x8 +#define WM8980_JACK1 0x9 +#define WM8980_DAC 0xa +#define WM8980_DACVOLL 0xb +#define WM8980_DACVOLR 0xc +#define WM8980_JACK2 0xd +#define WM8980_ADC 0xe +#define WM8980_ADCVOLL 0xf +#define WM8980_ADCVOLR 0x10 +#define WM8980_EQ1 0x12 +#define WM8980_EQ2 0x13 +#define WM8980_EQ3 0x14 +#define WM8980_EQ4 0x15 +#define WM8980_EQ5 0x16 +#define WM8980_DACLIM1 0x18 +#define WM8980_DACLIM2 0x19 +#define WM8980_NOTCH1 0x1b +#define WM8980_NOTCH2 0x1c +#define WM8980_NOTCH3 0x1d +#define WM8980_NOTCH4 0x1e +#define WM8980_ALC1 0x20 +#define WM8980_ALC2 0x21 +#define WM8980_ALC3 0x22 +#define WM8980_NGATE 0x23 +#define WM8980_PLLN 0x24 +#define WM8980_PLLK1 0x25 +#define WM8980_PLLK2 0x26 +#define WM8980_PLLK3 0x27 +#define WM8980_VIDEO 0x28 +#define WM8980_3D 0x29 +#define WM8980_BEEP 0x2b +#define WM8980_INPUT 0x2c +#define WM8980_INPPGAL 0x2d +#define WM8980_INPPGAR 0x2e +#define WM8980_ADCBOOSTL 0x2f +#define WM8980_ADCBOOSTR 0x30 +#define WM8980_OUTPUT 0x31 +#define WM8980_MIXL 0x32 +#define WM8980_MIXR 0x33 +#define WM8980_HPVOLL 0x34 +#define WM8980_HPVOLR 0x35 +#define WM8980_SPKVOLL 0x36 +#define WM8980_SPKVOLR 0x37 +#define WM8980_OUT3MIX 0x38 +#define WM8980_MONOMIX 0x39 + +#define WM8980_CACHEREGNUM 58 + +/* + * WM8980 Clock dividers + */ +#define WM8980_MCLKDIV 0 +#define WM8980_BCLKDIV 1 +#define WM8980_OPCLKDIV 2 +#define WM8980_DACOSR 3 +#define WM8980_ADCOSR 4 +#define WM8980_MCLKSEL 5 + +#define WM8980_MCLK_MCLK (0 << 8) +#define WM8980_MCLK_PLL (1 << 8) + +#define WM8980_MCLK_DIV_1 (0 << 5) +#define WM8980_MCLK_DIV_1_5 (1 << 5) +#define WM8980_MCLK_DIV_2 (2 << 5) +#define WM8980_MCLK_DIV_3 (3 << 5) +#define WM8980_MCLK_DIV_4 (4 << 5) +#define WM8980_MCLK_DIV_5_5 (5 << 5) +#define WM8980_MCLK_DIV_6 (6 << 5) + +#define WM8980_BCLK_DIV_1 (0 << 2) +#define WM8980_BCLK_DIV_2 (1 << 2) +#define WM8980_BCLK_DIV_4 (2 << 2) +#define WM8980_BCLK_DIV_8 (3 << 2) +#define WM8980_BCLK_DIV_16 (4 << 2) +#define WM8980_BCLK_DIV_32 (5 << 2) + +#define WM8980_DACOSR_64 (0 << 3) +#define WM8980_DACOSR_128 (1 << 3) + +#define WM8980_ADCOSR_64 (0 << 3) +#define WM8980_ADCOSR_128 (1 << 3) + +#define WM8980_OPCLK_DIV_1 (0 << 4) +#define WM8980_OPCLK_DIV_2 (1 << 4) +#define WM8980_OPCLK_DIV_3 (2 << 4) +#define WM8980_OPCLK_DIV_4 (3 << 4) + +struct wm8980_setup_data { + unsigned short i2c_address; +}; + +extern struct snd_soc_dai wm8980_dai; +extern struct snd_soc_codec_device soc_codec_dev_wm8980; + +#endif diff --git a/sound/soc/codecs/wm8990.c b/sound/soc/codecs/wm8990.c index a5731fa..cedf3f9 100644 --- a/sound/soc/codecs/wm8990.c +++ b/sound/soc/codecs/wm8990.c @@ -418,21 +418,6 @@ SOC_SINGLE("RIN34 Mute Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME, }; -/* add non dapm controls */ -static int wm8990_add_controls(struct snd_soc_codec *codec) -{ - int err, i; - - for (i = 0; i < ARRAY_SIZE(wm8990_snd_controls); i++) { - err = snd_ctl_add(codec->card, - snd_soc_cnew(&wm8990_snd_controls[i], codec, - NULL)); - if (err < 0) - return err; - } - return 0; -} - /* * _DAPM_ Controls */ @@ -1461,7 +1446,8 @@ static int wm8990_init(struct snd_soc_device *socdev) wm8990_write(codec, WM8990_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8)); wm8990_write(codec, WM8990_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8)); - wm8990_add_controls(codec); + snd_soc_add_controls(codec, wm8990_snd_controls, + ARRAY_SIZE(wm8990_snd_controls)); wm8990_add_widgets(codec); ret = snd_soc_init_card(socdev); if (ret < 0) { diff --git a/sound/soc/codecs/wm8991.c b/sound/soc/codecs/wm8991.c new file mode 100644 index 0000000..4d4e581 --- /dev/null +++ b/sound/soc/codecs/wm8991.c @@ -0,0 +1,1499 @@ +/* + * wm8991.c -- WM8991 ALSA Soc Audio driver + * + * Copyright 2007, 2008 Wolfson Microelectronics PLC. + * Author: Graeme Gregory + * linux@wolfsonmicro.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "wm8991.h" + +#define AUDIO_NAME "wm8991" +#define WM8991_VERSION "0.01" + +/* codec private data */ +struct wm8991_priv { + unsigned int sysclk; + unsigned int pcmclk; +}; + +/* + * wm8991 register cache + * We can't read the WM8991 register space when we + * are using 2 wire for device control, so we cache them instead. + */ +static const u16 wm8991_reg[] = WM8991_REGISTER_DEFAULTS; + +/* + * read wm8991 register cache + */ +static inline unsigned int wm8991_read_reg_cache(struct snd_soc_codec *codec, + unsigned int reg) +{ + u16 *cache = codec->reg_cache; + if (reg < 1 || reg > (ARRAY_SIZE(wm8991_reg) + 1)) + return -1; + return cache[reg - 1]; +} + +/* + * write wm8991 register cache + */ +static inline void wm8991_write_reg_cache(struct snd_soc_codec *codec, + unsigned int reg, unsigned int value) +{ + u16 *cache = codec->reg_cache; + if (reg < 1 || reg > 0x3f) + return; + cache[reg - 1] = value; +} + +/* + * write to the wm8991 register space + */ +static int wm8991_write(struct snd_soc_codec *codec, unsigned int reg, + unsigned int value) +{ + u8 data[3]; + + data[0] = reg & 0xFF; + data[1] = (value >> 8) & 0xFF; + data[2] = value & 0xFF; + + wm8991_write_reg_cache(codec, reg, value); + if (codec->hw_write(codec->control_data, data, 3) == 2) + return 0; + else + return -EIO; +} + +#define wm8991_reset(c) wm8991_write(c, WM8991_RESET, 0) + +static const unsigned int rec_mix_tlv[] = { + TLV_DB_RANGE_HEAD(1), + 0, 7, TLV_DB_LINEAR_ITEM(-1500, 600), +}; + +static const unsigned int in_pga_tlv[] = { + TLV_DB_RANGE_HEAD(1), + 0, 0x1F, TLV_DB_LINEAR_ITEM(-1650, 3000), +}; + +static const unsigned int out_mix_tlv[] = { + TLV_DB_RANGE_HEAD(1), + 0, 7, TLV_DB_LINEAR_ITEM(0, -2100), +}; + +static const unsigned int out_pga_tlv[] = { + TLV_DB_RANGE_HEAD(1), + 0, 127, TLV_DB_LINEAR_ITEM(-7300, 600), +}; + +static const unsigned int out_omix_tlv[] = { + TLV_DB_RANGE_HEAD(1), + 0, 7, TLV_DB_LINEAR_ITEM(-600, 0), +}; + +static const unsigned int out_dac_tlv[] = { + TLV_DB_RANGE_HEAD(1), + 0, 255, TLV_DB_LINEAR_ITEM(-7163, 0), +}; + +static const unsigned int in_adc_tlv[] = { + TLV_DB_RANGE_HEAD(1), + 0, 255, TLV_DB_LINEAR_ITEM(-7163, 1763), +}; + +static const unsigned int out_sidetone_tlv[] = { + TLV_DB_RANGE_HEAD(1), + 0, 31, TLV_DB_LINEAR_ITEM(-3600, 0), +}; + +static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + int reg = kcontrol->private_value & 0xff; + int ret; + u16 val; + + ret = snd_soc_put_volsw(kcontrol, ucontrol); + if (ret < 0) + return ret; + + /* now hit the volume update bits (always bit 8) */ + val = wm8991_read_reg_cache(codec, reg); + return wm8991_write(codec, reg, val | 0x0100); +} + +#define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert,\ + tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ + SNDRV_CTL_ELEM_ACCESS_READWRITE,\ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw, \ + .get = snd_soc_get_volsw, .put = wm899x_outpga_put_volsw_vu, \ + .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) } + + +static const char *wm8991_digital_sidetone[] = + {"None", "Left ADC", "Right ADC", "Reserved"}; + +static const struct soc_enum wm8991_left_digital_sidetone_enum = +SOC_ENUM_SINGLE(WM8991_DIGITAL_SIDE_TONE, + WM8991_ADC_TO_DACL_SHIFT, + WM8991_ADC_TO_DACL_MASK, + wm8991_digital_sidetone); + +static const struct soc_enum wm8991_right_digital_sidetone_enum = +SOC_ENUM_SINGLE(WM8991_DIGITAL_SIDE_TONE, + WM8991_ADC_TO_DACR_SHIFT, + WM8991_ADC_TO_DACR_MASK, + wm8991_digital_sidetone); + +static const char *wm8991_adcmode[] = + {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"}; + +static const struct soc_enum wm8991_right_adcmode_enum = +SOC_ENUM_SINGLE(WM8991_ADC_CTRL, + WM8991_ADC_HPF_CUT_SHIFT, + WM8991_ADC_HPF_CUT_MASK, + wm8991_adcmode); + +static const struct snd_kcontrol_new wm8991_snd_controls[] = { +/* INMIXL */ +SOC_SINGLE("LIN12 PGA Boost", WM8991_INPUT_MIXER3, WM8991_L12MNBST_BIT, 1, 0), +SOC_SINGLE("LIN34 PGA Boost", WM8991_INPUT_MIXER3, WM8991_L34MNBST_BIT, 1, 0), +/* INMIXR */ +SOC_SINGLE("RIN12 PGA Boost", WM8991_INPUT_MIXER3, WM8991_R12MNBST_BIT, 1, 0), +SOC_SINGLE("RIN34 PGA Boost", WM8991_INPUT_MIXER3, WM8991_R34MNBST_BIT, 1, 0), + +/* LOMIX */ +SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8991_OUTPUT_MIXER3, + WM8991_LLI3LOVOL_SHIFT, WM8991_LLI3LOVOL_MASK, 1, out_mix_tlv), +SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER3, + WM8991_LR12LOVOL_SHIFT, WM8991_LR12LOVOL_MASK, 1, out_mix_tlv), +SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER3, + WM8991_LL12LOVOL_SHIFT, WM8991_LL12LOVOL_MASK, 1, out_mix_tlv), +SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8991_OUTPUT_MIXER5, + WM8991_LRI3LOVOL_SHIFT, WM8991_LRI3LOVOL_MASK, 1, out_mix_tlv), +SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8991_OUTPUT_MIXER5, + WM8991_LRBLOVOL_SHIFT, WM8991_LRBLOVOL_MASK, 1, out_mix_tlv), +SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8991_OUTPUT_MIXER5, + WM8991_LRBLOVOL_SHIFT, WM8991_LRBLOVOL_MASK, 1, out_mix_tlv), + +/* ROMIX */ +SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8991_OUTPUT_MIXER4, + WM8991_RRI3ROVOL_SHIFT, WM8991_RRI3ROVOL_MASK, 1, out_mix_tlv), +SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER4, + WM8991_RL12ROVOL_SHIFT, WM8991_RL12ROVOL_MASK, 1, out_mix_tlv), +SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER4, + WM8991_RR12ROVOL_SHIFT, WM8991_RR12ROVOL_MASK, 1, out_mix_tlv), +SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8991_OUTPUT_MIXER6, + WM8991_RLI3ROVOL_SHIFT, WM8991_RLI3ROVOL_MASK, 1, out_mix_tlv), +SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8991_OUTPUT_MIXER6, + WM8991_RLBROVOL_SHIFT, WM8991_RLBROVOL_MASK, 1, out_mix_tlv), +SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8991_OUTPUT_MIXER6, + WM8991_RRBROVOL_SHIFT, WM8991_RRBROVOL_MASK, 1, out_mix_tlv), + +/* LOUT */ +SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8991_LEFT_OUTPUT_VOLUME, + WM8991_LOUTVOL_SHIFT, WM8991_LOUTVOL_MASK, 0, out_pga_tlv), +SOC_SINGLE("LOUT ZC", WM8991_LEFT_OUTPUT_VOLUME, WM8991_LOZC_BIT, 1, 0), + +/* ROUT */ +SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8991_RIGHT_OUTPUT_VOLUME, + WM8991_ROUTVOL_SHIFT, WM8991_ROUTVOL_MASK, 0, out_pga_tlv), +SOC_SINGLE("ROUT ZC", WM8991_RIGHT_OUTPUT_VOLUME, WM8991_ROZC_BIT, 1, 0), + +/* LOPGA */ +SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8991_LEFT_OPGA_VOLUME, + WM8991_LOPGAVOL_SHIFT, WM8991_LOPGAVOL_MASK, 0, out_pga_tlv), +SOC_SINGLE("LOPGA ZC Switch", WM8991_LEFT_OPGA_VOLUME, + WM8991_LOPGAZC_BIT, 1, 0), + +/* ROPGA */ +SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8991_RIGHT_OPGA_VOLUME, + WM8991_ROPGAVOL_SHIFT, WM8991_ROPGAVOL_MASK, 0, out_pga_tlv), +SOC_SINGLE("ROPGA ZC Switch", WM8991_RIGHT_OPGA_VOLUME, + WM8991_ROPGAZC_BIT, 1, 0), + +SOC_SINGLE("LON Mute Switch", WM8991_LINE_OUTPUTS_VOLUME, + WM8991_LONMUTE_BIT, 1, 0), +SOC_SINGLE("LOP Mute Switch", WM8991_LINE_OUTPUTS_VOLUME, + WM8991_LOPMUTE_BIT, 1, 0), +SOC_SINGLE("LOP Attenuation Switch", WM8991_LINE_OUTPUTS_VOLUME, + WM8991_LOATTN_BIT, 1, 0), +SOC_SINGLE("RON Mute Switch", WM8991_LINE_OUTPUTS_VOLUME, + WM8991_RONMUTE_BIT, 1, 0), +SOC_SINGLE("ROP Mute Switch", WM8991_LINE_OUTPUTS_VOLUME, + WM8991_ROPMUTE_BIT, 1, 0), +SOC_SINGLE("ROP Attenuation Switch", WM8991_LINE_OUTPUTS_VOLUME, + WM8991_ROATTN_BIT, 1, 0), + +SOC_SINGLE("OUT3 Mute Switch", WM8991_OUT3_4_VOLUME, + WM8991_OUT3MUTE_BIT, 1, 0), +SOC_SINGLE("OUT3 Attenuation Switch", WM8991_OUT3_4_VOLUME, + WM8991_OUT3ATTN_BIT, 1, 0), + +SOC_SINGLE("OUT4 Mute Switch", WM8991_OUT3_4_VOLUME, + WM8991_OUT4MUTE_BIT, 1, 0), +SOC_SINGLE("OUT4 Attenuation Switch", WM8991_OUT3_4_VOLUME, + WM8991_OUT4ATTN_BIT, 1, 0), + +SOC_SINGLE("Speaker Mode Switch", WM8991_CLASSD1, + WM8991_CDMODE_BIT, 1, 0), + +SOC_SINGLE("Speaker Output Attenuation Volume", WM8991_SPEAKER_VOLUME, + WM8991_SPKVOL_SHIFT, WM8991_SPKVOL_MASK, 0), +SOC_SINGLE("Speaker DC Boost Volume", WM8991_CLASSD3, + WM8991_DCGAIN_SHIFT, WM8991_DCGAIN_MASK, 0), +SOC_SINGLE("Speaker AC Boost Volume", WM8991_CLASSD3, + WM8991_ACGAIN_SHIFT, WM8991_ACGAIN_MASK, 0), + +SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume", + WM8991_LEFT_DAC_DIGITAL_VOLUME, + WM8991_DACL_VOL_SHIFT, + WM8991_DACL_VOL_MASK, + 0, + out_dac_tlv), + +SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume", + WM8991_RIGHT_DAC_DIGITAL_VOLUME, + WM8991_DACR_VOL_SHIFT, + WM8991_DACR_VOL_MASK, + 0, + out_dac_tlv), + +SOC_ENUM("Left Digital Sidetone", wm8991_left_digital_sidetone_enum), +SOC_ENUM("Right Digital Sidetone", wm8991_right_digital_sidetone_enum), + +SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8991_DIGITAL_SIDE_TONE, + WM8991_ADCL_DAC_SVOL_SHIFT, WM8991_ADCL_DAC_SVOL_MASK, 0, + out_sidetone_tlv), +SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8991_DIGITAL_SIDE_TONE, + WM8991_ADCR_DAC_SVOL_SHIFT, WM8991_ADCR_DAC_SVOL_MASK, 0, + out_sidetone_tlv), + +SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8991_ADC_CTRL, + WM8991_ADC_HPF_ENA_BIT, 1, 0), + +SOC_ENUM("ADC HPF Mode", wm8991_right_adcmode_enum), + +SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume", + WM8991_LEFT_ADC_DIGITAL_VOLUME, + WM8991_ADCL_VOL_SHIFT, + WM8991_ADCL_VOL_MASK, + 0, + in_adc_tlv), + +SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume", + WM8991_RIGHT_ADC_DIGITAL_VOLUME, + WM8991_ADCR_VOL_SHIFT, + WM8991_ADCR_VOL_MASK, + 0, + in_adc_tlv), + +SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN12 Volume", + WM8991_LEFT_LINE_INPUT_1_2_VOLUME, + WM8991_LIN12VOL_SHIFT, + WM8991_LIN12VOL_MASK, + 0, + in_pga_tlv), + +SOC_SINGLE("LIN12 ZC Switch", WM8991_LEFT_LINE_INPUT_1_2_VOLUME, + WM8991_LI12ZC_BIT, 1, 0), + +SOC_SINGLE("LIN12 Mute Switch", WM8991_LEFT_LINE_INPUT_1_2_VOLUME, + WM8991_LI12MUTE_BIT, 1, 0), + +SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN34 Volume", + WM8991_LEFT_LINE_INPUT_3_4_VOLUME, + WM8991_LIN34VOL_SHIFT, + WM8991_LIN34VOL_MASK, + 0, + in_pga_tlv), + +SOC_SINGLE("LIN34 ZC Switch", WM8991_LEFT_LINE_INPUT_3_4_VOLUME, + WM8991_LI34ZC_BIT, 1, 0), + +SOC_SINGLE("LIN34 Mute Switch", WM8991_LEFT_LINE_INPUT_3_4_VOLUME, + WM8991_LI34MUTE_BIT, 1, 0), + +SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN12 Volume", + WM8991_RIGHT_LINE_INPUT_1_2_VOLUME, + WM8991_RIN12VOL_SHIFT, + WM8991_RIN12VOL_MASK, + 0, + in_pga_tlv), + +SOC_SINGLE("RIN12 ZC Switch", WM8991_RIGHT_LINE_INPUT_1_2_VOLUME, + WM8991_RI12ZC_BIT, 1, 0), + +SOC_SINGLE("RIN12 Mute Switch", WM8991_RIGHT_LINE_INPUT_1_2_VOLUME, + WM8991_RI12MUTE_BIT, 1, 0), + +SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN34 Volume", + WM8991_RIGHT_LINE_INPUT_3_4_VOLUME, + WM8991_RIN34VOL_SHIFT, + WM8991_RIN34VOL_MASK, + 0, + in_pga_tlv), + +SOC_SINGLE("RIN34 ZC Switch", WM8991_RIGHT_LINE_INPUT_3_4_VOLUME, + WM8991_RI34ZC_BIT, 1, 0), + +SOC_SINGLE("RIN34 Mute Switch", WM8991_RIGHT_LINE_INPUT_3_4_VOLUME, + WM8991_RI34MUTE_BIT, 1, 0), + +}; + +/* add non dapm controls */ +static int wm8991_add_controls(struct snd_soc_codec *codec) +{ + int err, i; + + for (i = 0; i < ARRAY_SIZE(wm8991_snd_controls); i++) { + err = snd_ctl_add(codec->card, + snd_soc_cnew(&wm8991_snd_controls[i], codec, + NULL)); + if (err < 0) + return err; + } + return 0; +} + +/* + * _DAPM_ Controls + */ + +static int inmixer_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + u16 reg, fakepower; + + reg = wm8991_read_reg_cache(w->codec, WM8991_POWER_MANAGEMENT_2); + fakepower = wm8991_read_reg_cache(w->codec, WM8991_INTDRIVBITS); + + if (fakepower & ((1 << WM8991_INMIXL_PWR_BIT) | + (1 << WM8991_AINLMUX_PWR_BIT))) { + reg |= WM8991_AINL_ENA; + } else { + reg &= ~WM8991_AINL_ENA; + } + + if (fakepower & ((1 << WM8991_INMIXR_PWR_BIT) | + (1 << WM8991_AINRMUX_PWR_BIT))) { + reg |= WM8991_AINR_ENA; + } else { + reg &= ~WM8991_AINL_ENA; + } + wm8991_write(w->codec, WM8991_POWER_MANAGEMENT_2, reg); + + return 0; +} + +static int outmixer_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + u32 reg_shift = kcontrol->private_value & 0xfff; + int ret = 0; + u16 reg; + + switch (reg_shift) { + case WM8991_SPEAKER_MIXER | (WM8991_LDSPK_BIT << 8): + reg = wm8991_read_reg_cache(w->codec, WM8991_OUTPUT_MIXER1); + if (reg & WM8991_LDLO) { + printk(KERN_WARNING + "Cannot set as Output Mixer 1 LDLO Set\n"); + ret = -1; + } + break; + + case WM8991_SPEAKER_MIXER | (WM8991_RDSPK_BIT << 8): + reg = wm8991_read_reg_cache(w->codec, WM8991_OUTPUT_MIXER2); + if (reg & WM8991_RDRO) { + printk(KERN_WARNING + "Cannot set as Output Mixer 2 RDRO Set\n"); + ret = -1; + } + break; + + case WM8991_OUTPUT_MIXER1 | (WM8991_LDLO_BIT << 8): + reg = wm8991_read_reg_cache(w->codec, WM8991_SPEAKER_MIXER); + if (reg & WM8991_LDSPK) { + printk(KERN_WARNING + "Cannot set as Speaker Mixer LDSPK Set\n"); + ret = -1; + } + break; + + case WM8991_OUTPUT_MIXER2 | (WM8991_RDRO_BIT << 8): + reg = wm8991_read_reg_cache(w->codec, WM8991_SPEAKER_MIXER); + if (reg & WM8991_RDSPK) { + printk(KERN_WARNING + "Cannot set as Speaker Mixer RDSPK Set\n"); + ret = -1; + } + break; + + default: + BUG(); + } + + return ret; +} + +/* INMIX dB values */ +static const unsigned int in_mix_tlv[] = { + TLV_DB_RANGE_HEAD(1), + 0, 7, TLV_DB_LINEAR_ITEM(-1200, 600), +}; + +/* Left In PGA Connections */ +static const struct snd_kcontrol_new wm8991_dapm_lin12_pga_controls[] = { +SOC_DAPM_SINGLE("LIN1 Switch", WM8991_INPUT_MIXER2, WM8991_LMN1_BIT, 1, 0), +SOC_DAPM_SINGLE("LIN2 Switch", WM8991_INPUT_MIXER2, WM8991_LMP2_BIT, 1, 0), +}; + +static const struct snd_kcontrol_new wm8991_dapm_lin34_pga_controls[] = { +SOC_DAPM_SINGLE("LIN3 Switch", WM8991_INPUT_MIXER2, WM8991_LMN3_BIT, 1, 0), +SOC_DAPM_SINGLE("LIN4 Switch", WM8991_INPUT_MIXER2, WM8991_LMP4_BIT, 1, 0), +}; + +/* Right In PGA Connections */ +static const struct snd_kcontrol_new wm8991_dapm_rin12_pga_controls[] = { +SOC_DAPM_SINGLE("RIN1 Switch", WM8991_INPUT_MIXER2, WM8991_RMN1_BIT, 1, 0), +SOC_DAPM_SINGLE("RIN2 Switch", WM8991_INPUT_MIXER2, WM8991_RMP2_BIT, 1, 0), +}; + +static const struct snd_kcontrol_new wm8991_dapm_rin34_pga_controls[] = { +SOC_DAPM_SINGLE("RIN3 Switch", WM8991_INPUT_MIXER2, WM8991_RMN3_BIT, 1, 0), +SOC_DAPM_SINGLE("RIN4 Switch", WM8991_INPUT_MIXER2, WM8991_RMP4_BIT, 1, 0), +}; + +/* INMIXL */ +static const struct snd_kcontrol_new wm8991_dapm_inmixl_controls[] = { +SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8991_INPUT_MIXER3, + WM8991_LDBVOL_SHIFT, WM8991_LDBVOL_MASK, 0, in_mix_tlv), +SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8991_INPUT_MIXER5, WM8991_LI2BVOL_SHIFT, + 7, 0, in_mix_tlv), +SOC_DAPM_SINGLE("LINPGA12 Switch", WM8991_INPUT_MIXER3, WM8991_L12MNB_BIT, + 1, 0), +SOC_DAPM_SINGLE("LINPGA34 Switch", WM8991_INPUT_MIXER3, WM8991_L34MNB_BIT, + 1, 0), +}; + +/* INMIXR */ +static const struct snd_kcontrol_new wm8991_dapm_inmixr_controls[] = { +SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8991_INPUT_MIXER4, + WM8991_RDBVOL_SHIFT, WM8991_RDBVOL_MASK, 0, in_mix_tlv), +SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8991_INPUT_MIXER6, WM8991_RI2BVOL_SHIFT, + 7, 0, in_mix_tlv), +SOC_DAPM_SINGLE("RINPGA12 Switch", WM8991_INPUT_MIXER3, WM8991_L12MNB_BIT, + 1, 0), +SOC_DAPM_SINGLE("RINPGA34 Switch", WM8991_INPUT_MIXER3, WM8991_L34MNB_BIT, + 1, 0), +}; + +/* AINLMUX */ +static const char *wm8991_ainlmux[] = + {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"}; + +static const struct soc_enum wm8991_ainlmux_enum = +SOC_ENUM_SINGLE(WM8991_INPUT_MIXER1, WM8991_AINLMODE_SHIFT, + ARRAY_SIZE(wm8991_ainlmux), wm8991_ainlmux); + +static const struct snd_kcontrol_new wm8991_dapm_ainlmux_controls = +SOC_DAPM_ENUM("Route", wm8991_ainlmux_enum); + +/* DIFFINL */ + +/* AINRMUX */ +static const char *wm8991_ainrmux[] = + {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"}; + +static const struct soc_enum wm8991_ainrmux_enum = +SOC_ENUM_SINGLE(WM8991_INPUT_MIXER1, WM8991_AINRMODE_SHIFT, + ARRAY_SIZE(wm8991_ainrmux), wm8991_ainrmux); + +static const struct snd_kcontrol_new wm8991_dapm_ainrmux_controls = +SOC_DAPM_ENUM("Route", wm8991_ainrmux_enum); + +/* RXVOICE */ +static const struct snd_kcontrol_new wm8991_dapm_rxvoice_controls[] = { +SOC_DAPM_SINGLE_TLV("LIN4/RXN", WM8991_INPUT_MIXER5, WM8991_LR4BVOL_SHIFT, + WM8991_LR4BVOL_MASK, 0, in_mix_tlv), +SOC_DAPM_SINGLE_TLV("RIN4/RXP", WM8991_INPUT_MIXER6, WM8991_RL4BVOL_SHIFT, + WM8991_RL4BVOL_MASK, 0, in_mix_tlv), +}; + +/* LOMIX */ +static const struct snd_kcontrol_new wm8991_dapm_lomix_controls[] = { +SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8991_OUTPUT_MIXER1, + WM8991_LRBLO_BIT, 1, 0), +SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8991_OUTPUT_MIXER1, + WM8991_LLBLO_BIT, 1, 0), +SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8991_OUTPUT_MIXER1, + WM8991_LRI3LO_BIT, 1, 0), +SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8991_OUTPUT_MIXER1, + WM8991_LLI3LO_BIT, 1, 0), +SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER1, + WM8991_LR12LO_BIT, 1, 0), +SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER1, + WM8991_LL12LO_BIT, 1, 0), +SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8991_OUTPUT_MIXER1, + WM8991_LDLO_BIT, 1, 0), +}; + +/* ROMIX */ +static const struct snd_kcontrol_new wm8991_dapm_romix_controls[] = { +SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8991_OUTPUT_MIXER2, + WM8991_RLBRO_BIT, 1, 0), +SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8991_OUTPUT_MIXER2, + WM8991_RRBRO_BIT, 1, 0), +SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8991_OUTPUT_MIXER2, + WM8991_RLI3RO_BIT, 1, 0), +SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8991_OUTPUT_MIXER2, + WM8991_RRI3RO_BIT, 1, 0), +SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER2, + WM8991_RL12RO_BIT, 1, 0), +SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER2, + WM8991_RR12RO_BIT, 1, 0), +SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8991_OUTPUT_MIXER2, + WM8991_RDRO_BIT, 1, 0), +}; + +/* LONMIX */ +static const struct snd_kcontrol_new wm8991_dapm_lonmix_controls[] = { +SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8991_LINE_MIXER1, + WM8991_LLOPGALON_BIT, 1, 0), +SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8991_LINE_MIXER1, + WM8991_LROPGALON_BIT, 1, 0), +SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8991_LINE_MIXER1, + WM8991_LOPLON_BIT, 1, 0), +}; + +/* LOPMIX */ +static const struct snd_kcontrol_new wm8991_dapm_lopmix_controls[] = { +SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8991_LINE_MIXER1, + WM8991_LR12LOP_BIT, 1, 0), +SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8991_LINE_MIXER1, + WM8991_LL12LOP_BIT, 1, 0), +SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8991_LINE_MIXER1, + WM8991_LLOPGALOP_BIT, 1, 0), +}; + +/* RONMIX */ +static const struct snd_kcontrol_new wm8991_dapm_ronmix_controls[] = { +SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8991_LINE_MIXER2, + WM8991_RROPGARON_BIT, 1, 0), +SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8991_LINE_MIXER2, + WM8991_RLOPGARON_BIT, 1, 0), +SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8991_LINE_MIXER2, + WM8991_ROPRON_BIT, 1, 0), +}; + +/* ROPMIX */ +static const struct snd_kcontrol_new wm8991_dapm_ropmix_controls[] = { +SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8991_LINE_MIXER2, + WM8991_RL12ROP_BIT, 1, 0), +SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8991_LINE_MIXER2, + WM8991_RR12ROP_BIT, 1, 0), +SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8991_LINE_MIXER2, + WM8991_RROPGAROP_BIT, 1, 0), +}; + +/* OUT3MIX */ +static const struct snd_kcontrol_new wm8991_dapm_out3mix_controls[] = { +SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8991_OUT3_4_MIXER, + WM8991_LI4O3_BIT, 1, 0), +SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8991_OUT3_4_MIXER, + WM8991_LPGAO3_BIT, 1, 0), +}; + +/* OUT4MIX */ +static const struct snd_kcontrol_new wm8991_dapm_out4mix_controls[] = { +SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8991_OUT3_4_MIXER, + WM8991_RPGAO4_BIT, 1, 0), +SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8991_OUT3_4_MIXER, + WM8991_RI4O4_BIT, 1, 0), +}; + +/* SPKMIX */ +static const struct snd_kcontrol_new wm8991_dapm_spkmix_controls[] = { +SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8991_SPEAKER_MIXER, + WM8991_LI2SPK_BIT, 1, 0), +SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8991_SPEAKER_MIXER, + WM8991_LB2SPK_BIT, 1, 0), +SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8991_SPEAKER_MIXER, + WM8991_LOPGASPK_BIT, 1, 0), +SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8991_SPEAKER_MIXER, + WM8991_LDSPK_BIT, 1, 0), +SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8991_SPEAKER_MIXER, + WM8991_RDSPK_BIT, 1, 0), +SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8991_SPEAKER_MIXER, + WM8991_ROPGASPK_BIT, 1, 0), +SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8991_SPEAKER_MIXER, + WM8991_RL12ROP_BIT, 1, 0), +SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8991_SPEAKER_MIXER, + WM8991_RI2SPK_BIT, 1, 0), +}; + +static const struct snd_soc_dapm_widget wm8991_dapm_widgets[] = { +/* Input Side */ +/* Input Lines */ +SND_SOC_DAPM_INPUT("LIN1"), +SND_SOC_DAPM_INPUT("LIN2"), +SND_SOC_DAPM_INPUT("LIN3"), +SND_SOC_DAPM_INPUT("LIN4/RXN"), +SND_SOC_DAPM_INPUT("RIN3"), +SND_SOC_DAPM_INPUT("RIN4/RXP"), +SND_SOC_DAPM_INPUT("RIN1"), +SND_SOC_DAPM_INPUT("RIN2"), +SND_SOC_DAPM_INPUT("Internal ADC Source"), + +/* DACs */ +SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8991_POWER_MANAGEMENT_2, + WM8991_ADCL_ENA_BIT, 0), +SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8991_POWER_MANAGEMENT_2, + WM8991_ADCR_ENA_BIT, 0), + +/* Input PGAs */ +SND_SOC_DAPM_MIXER("LIN12 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_LIN12_ENA_BIT, + 0, &wm8991_dapm_lin12_pga_controls[0], + ARRAY_SIZE(wm8991_dapm_lin12_pga_controls)), +SND_SOC_DAPM_MIXER("LIN34 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_LIN34_ENA_BIT, + 0, &wm8991_dapm_lin34_pga_controls[0], + ARRAY_SIZE(wm8991_dapm_lin34_pga_controls)), +SND_SOC_DAPM_MIXER("RIN12 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_RIN12_ENA_BIT, + 0, &wm8991_dapm_rin12_pga_controls[0], + ARRAY_SIZE(wm8991_dapm_rin12_pga_controls)), +SND_SOC_DAPM_MIXER("RIN34 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_RIN34_ENA_BIT, + 0, &wm8991_dapm_rin34_pga_controls[0], + ARRAY_SIZE(wm8991_dapm_rin34_pga_controls)), + +/* INMIXL */ +SND_SOC_DAPM_MIXER_E("INMIXL", WM8991_INTDRIVBITS, WM8991_INMIXL_PWR_BIT, 0, + &wm8991_dapm_inmixl_controls[0], + ARRAY_SIZE(wm8991_dapm_inmixl_controls), + inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + +/* AINLMUX */ +SND_SOC_DAPM_MUX_E("AILNMUX", WM8991_INTDRIVBITS, WM8991_AINLMUX_PWR_BIT, 0, + &wm8991_dapm_ainlmux_controls, inmixer_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + +/* INMIXR */ +SND_SOC_DAPM_MIXER_E("INMIXR", WM8991_INTDRIVBITS, WM8991_INMIXR_PWR_BIT, 0, + &wm8991_dapm_inmixr_controls[0], + ARRAY_SIZE(wm8991_dapm_inmixr_controls), + inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + +/* AINRMUX */ +SND_SOC_DAPM_MUX_E("AIRNMUX", WM8991_INTDRIVBITS, WM8991_AINRMUX_PWR_BIT, 0, + &wm8991_dapm_ainrmux_controls, inmixer_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + +/* Output Side */ +/* DACs */ +SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8991_POWER_MANAGEMENT_3, + WM8991_DACL_ENA_BIT, 0), +SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8991_POWER_MANAGEMENT_3, + WM8991_DACR_ENA_BIT, 0), + +/* LOMIX */ +SND_SOC_DAPM_MIXER_E("LOMIX", WM8991_POWER_MANAGEMENT_3, WM8991_LOMIX_ENA_BIT, + 0, &wm8991_dapm_lomix_controls[0], + ARRAY_SIZE(wm8991_dapm_lomix_controls), + outmixer_event, SND_SOC_DAPM_PRE_REG), + +/* LONMIX */ +SND_SOC_DAPM_MIXER("LONMIX", WM8991_POWER_MANAGEMENT_3, WM8991_LON_ENA_BIT, 0, + &wm8991_dapm_lonmix_controls[0], + ARRAY_SIZE(wm8991_dapm_lonmix_controls)), + +/* LOPMIX */ +SND_SOC_DAPM_MIXER("LOPMIX", WM8991_POWER_MANAGEMENT_3, WM8991_LOP_ENA_BIT, 0, + &wm8991_dapm_lopmix_controls[0], + ARRAY_SIZE(wm8991_dapm_lopmix_controls)), + +/* OUT3MIX */ +SND_SOC_DAPM_MIXER("OUT3MIX", WM8991_POWER_MANAGEMENT_1, WM8991_OUT3_ENA_BIT, 0, + &wm8991_dapm_out3mix_controls[0], + ARRAY_SIZE(wm8991_dapm_out3mix_controls)), + +/* SPKMIX */ +SND_SOC_DAPM_MIXER_E("SPKMIX", WM8991_POWER_MANAGEMENT_1, WM8991_SPK_ENA_BIT, 0, + &wm8991_dapm_spkmix_controls[0], + ARRAY_SIZE(wm8991_dapm_spkmix_controls), outmixer_event, + SND_SOC_DAPM_PRE_REG), + +/* OUT4MIX */ +SND_SOC_DAPM_MIXER("OUT4MIX", WM8991_POWER_MANAGEMENT_1, WM8991_OUT4_ENA_BIT, 0, + &wm8991_dapm_out4mix_controls[0], + ARRAY_SIZE(wm8991_dapm_out4mix_controls)), + +/* ROPMIX */ +SND_SOC_DAPM_MIXER("ROPMIX", WM8991_POWER_MANAGEMENT_3, WM8991_ROP_ENA_BIT, 0, + &wm8991_dapm_ropmix_controls[0], + ARRAY_SIZE(wm8991_dapm_ropmix_controls)), + +/* RONMIX */ +SND_SOC_DAPM_MIXER("RONMIX", WM8991_POWER_MANAGEMENT_3, WM8991_RON_ENA_BIT, 0, + &wm8991_dapm_ronmix_controls[0], + ARRAY_SIZE(wm8991_dapm_ronmix_controls)), + +/* ROMIX */ +SND_SOC_DAPM_MIXER_E("ROMIX", WM8991_POWER_MANAGEMENT_3, WM8991_ROMIX_ENA_BIT, + 0, &wm8991_dapm_romix_controls[0], + ARRAY_SIZE(wm8991_dapm_romix_controls), + outmixer_event, SND_SOC_DAPM_PRE_REG), + +/* LOUT PGA */ +SND_SOC_DAPM_PGA("LOUT PGA", WM8991_POWER_MANAGEMENT_1, WM8991_LOUT_ENA_BIT, 0, + NULL, 0), + +/* ROUT PGA */ +SND_SOC_DAPM_PGA("ROUT PGA", WM8991_POWER_MANAGEMENT_1, WM8991_ROUT_ENA_BIT, 0, + NULL, 0), + +/* LOPGA */ +SND_SOC_DAPM_PGA("LOPGA", WM8991_POWER_MANAGEMENT_3, WM8991_LOPGA_ENA_BIT, 0, + NULL, 0), + +/* ROPGA */ +SND_SOC_DAPM_PGA("ROPGA", WM8991_POWER_MANAGEMENT_3, WM8991_ROPGA_ENA_BIT, 0, + NULL, 0), + +/* MICBIAS */ +SND_SOC_DAPM_MICBIAS("MICBIAS", WM8991_POWER_MANAGEMENT_1, + WM8991_MICBIAS_ENA_BIT, 0), + +SND_SOC_DAPM_OUTPUT("LON"), +SND_SOC_DAPM_OUTPUT("LOP"), +SND_SOC_DAPM_OUTPUT("OUT3"), +SND_SOC_DAPM_OUTPUT("LOUT"), +SND_SOC_DAPM_OUTPUT("SPKN"), +SND_SOC_DAPM_OUTPUT("SPKP"), +SND_SOC_DAPM_OUTPUT("ROUT"), +SND_SOC_DAPM_OUTPUT("OUT4"), +SND_SOC_DAPM_OUTPUT("ROP"), +SND_SOC_DAPM_OUTPUT("RON"), + +SND_SOC_DAPM_OUTPUT("Internal DAC Sink"), +}; + +static const struct snd_soc_dapm_route audio_map[] = { + /* Make DACs turn on when playing even if not mixed into any outputs */ + {"Internal DAC Sink", NULL, "Left DAC"}, + {"Internal DAC Sink", NULL, "Right DAC"}, + + /* Make ADCs turn on when recording even if not mixed from any inputs */ + {"Left ADC", NULL, "Internal ADC Source"}, + {"Right ADC", NULL, "Internal ADC Source"}, + + /* Input Side */ + /* LIN12 PGA */ + {"LIN12 PGA", "LIN1 Switch", "LIN1"}, + {"LIN12 PGA", "LIN2 Switch", "LIN2"}, + /* LIN34 PGA */ + {"LIN34 PGA", "LIN3 Switch", "LIN3"}, + {"LIN34 PGA", "LIN4 Switch", "LIN4"}, + /* INMIXL */ + {"INMIXL", "Record Left Volume", "LOMIX"}, + {"INMIXL", "LIN2 Volume", "LIN2"}, + {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"}, + {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"}, + /* AILNMUX */ + {"AILNMUX", "INMIXL Mix", "INMIXL"}, + {"AILNMUX", "DIFFINL Mix", "LIN12PGA"}, + {"AILNMUX", "DIFFINL Mix", "LIN34PGA"}, + {"AILNMUX", "RXVOICE Mix", "LIN4/RXN"}, + {"AILNMUX", "RXVOICE Mix", "RIN4/RXP"}, + /* ADC */ + {"Left ADC", NULL, "AILNMUX"}, + + /* RIN12 PGA */ + {"RIN12 PGA", "RIN1 Switch", "RIN1"}, + {"RIN12 PGA", "RIN2 Switch", "RIN2"}, + /* RIN34 PGA */ + {"RIN34 PGA", "RIN3 Switch", "RIN3"}, + {"RIN34 PGA", "RIN4 Switch", "RIN4"}, + /* INMIXL */ + {"INMIXR", "Record Right Volume", "ROMIX"}, + {"INMIXR", "RIN2 Volume", "RIN2"}, + {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"}, + {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"}, + /* AIRNMUX */ + {"AIRNMUX", "INMIXR Mix", "INMIXR"}, + {"AIRNMUX", "DIFFINR Mix", "RIN12PGA"}, + {"AIRNMUX", "DIFFINR Mix", "RIN34PGA"}, + {"AIRNMUX", "RXVOICE Mix", "RIN4/RXN"}, + {"AIRNMUX", "RXVOICE Mix", "RIN4/RXP"}, + /* ADC */ + {"Right ADC", NULL, "AIRNMUX"}, + + /* LOMIX */ + {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"}, + {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"}, + {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"}, + {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"}, + {"LOMIX", "LOMIX Right ADC Bypass Switch", "AINRMUX"}, + {"LOMIX", "LOMIX Left ADC Bypass Switch", "AINLMUX"}, + {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"}, + + /* ROMIX */ + {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"}, + {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"}, + {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"}, + {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"}, + {"ROMIX", "ROMIX Right ADC Bypass Switch", "AINRMUX"}, + {"ROMIX", "ROMIX Left ADC Bypass Switch", "AINLMUX"}, + {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"}, + + /* SPKMIX */ + {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"}, + {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"}, + {"SPKMIX", "SPKMIX LADC Bypass Switch", "AINLMUX"}, + {"SPKMIX", "SPKMIX RADC Bypass Switch", "AINRMUX"}, + {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"}, + {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"}, + {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"}, + {"SPKMIX", "SPKMIX Left DAC Switch", "Right DAC"}, + + /* LONMIX */ + {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"}, + {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"}, + {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"}, + + /* LOPMIX */ + {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"}, + {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"}, + {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"}, + + /* OUT3MIX */ + {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXP"}, + {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"}, + + /* OUT4MIX */ + {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"}, + {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"}, + + /* RONMIX */ + {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"}, + {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"}, + {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"}, + + /* ROPMIX */ + {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"}, + {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"}, + {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"}, + + /* Out Mixer PGAs */ + {"LOPGA", NULL, "LOMIX"}, + {"ROPGA", NULL, "ROMIX"}, + + {"LOUT PGA", NULL, "LOMIX"}, + {"ROUT PGA", NULL, "ROMIX"}, + + /* Output Pins */ + {"LON", NULL, "LONMIX"}, + {"LOP", NULL, "LOPMIX"}, + {"OUT", NULL, "OUT3MIX"}, + {"LOUT", NULL, "LOUT PGA"}, + {"SPKN", NULL, "SPKMIX"}, + {"ROUT", NULL, "ROUT PGA"}, + {"OUT4", NULL, "OUT4MIX"}, + {"ROP", NULL, "ROPMIX"}, + {"RON", NULL, "RONMIX"}, +}; + +static int wm8991_add_widgets(struct snd_soc_codec *codec) +{ + snd_soc_dapm_new_controls(codec, wm8991_dapm_widgets, + ARRAY_SIZE(wm8991_dapm_widgets)); + + snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + + snd_soc_dapm_new_widgets(codec); + return 0; +} + +/* PLL divisors */ +struct _pll_div { + u32 div2; + u32 n; + u32 k; +}; + +/* The size in bits of the pll divide multiplied by 10 + * to allow rounding later */ +#define FIXED_PLL_SIZE ((1 << 16) * 10) + +static void pll_factors(struct _pll_div *pll_div, unsigned int target, + unsigned int source) +{ + u64 Kpart; + unsigned int K, Ndiv, Nmod; + + + Ndiv = target / source; + if (Ndiv < 6) { + source >>= 1; + pll_div->div2 = 1; + Ndiv = target / source; + } else + pll_div->div2 = 0; + + if ((Ndiv < 6) || (Ndiv > 12)) + printk(KERN_WARNING + "WM8991 N value outwith recommended range! N = %d\n", Ndiv); + + pll_div->n = Ndiv; + Nmod = target % source; + Kpart = FIXED_PLL_SIZE * (long long)Nmod; + + do_div(Kpart, source); + + K = Kpart & 0xFFFFFFFF; + + /* Check if we need to round */ + if ((K % 10) >= 5) + K += 5; + + /* Move down to proper range now rounding is done */ + K /= 10; + + pll_div->k = K; +} + +static int wm8991_set_dai_pll(struct snd_soc_dai *codec_dai, + int pll_id, unsigned int freq_in, unsigned int freq_out) +{ + u16 reg; + struct snd_soc_codec *codec = codec_dai->codec; + struct _pll_div pll_div; + + if (freq_in && freq_out) { + pll_factors(&pll_div, freq_out * 4, freq_in); + + /* Turn on PLL */ + reg = wm8991_read_reg_cache(codec, WM8991_POWER_MANAGEMENT_2); + reg |= WM8991_PLL_ENA; + wm8991_write(codec, WM8991_POWER_MANAGEMENT_2, reg); + + /* sysclk comes from PLL */ + reg = wm8991_read_reg_cache(codec, WM8991_CLOCKING_2); + wm8991_write(codec, WM8991_CLOCKING_2, reg | WM8991_SYSCLK_SRC); + + /* set up N , fractional mode and pre-divisor if neccessary */ + wm8991_write(codec, WM8991_PLL1, pll_div.n | WM8991_SDM | + (pll_div.div2 ? WM8991_PRESCALE : 0)); + wm8991_write(codec, WM8991_PLL2, (u8)(pll_div.k>>8)); + wm8991_write(codec, WM8991_PLL3, (u8)(pll_div.k & 0xFF)); + } else { + /* Turn on PLL */ + reg = wm8991_read_reg_cache(codec, WM8991_POWER_MANAGEMENT_2); + reg &= ~WM8991_PLL_ENA; + wm8991_write(codec, WM8991_POWER_MANAGEMENT_2, reg); + } + return 0; +} + +/* + * Clock after PLL and dividers + */ +static int wm8991_set_dai_sysclk(struct snd_soc_dai *codec_dai, + int clk_id, unsigned int freq, int dir) +{ + struct snd_soc_codec *codec = codec_dai->codec; + struct wm8991_priv *wm8991 = codec->private_data; + + wm8991->sysclk = freq; + return 0; +} + +/* + * Set's ADC and Voice DAC format. + */ +static int wm8991_set_dai_fmt(struct snd_soc_dai *codec_dai, + unsigned int fmt) +{ + struct snd_soc_codec *codec = codec_dai->codec; + u16 audio1, audio3; + + audio1 = wm8991_read_reg_cache(codec, WM8991_AUDIO_INTERFACE_1); + audio3 = wm8991_read_reg_cache(codec, WM8991_AUDIO_INTERFACE_3); + + /* set master/slave audio interface */ + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBS_CFS: + audio3 &= ~WM8991_AIF_MSTR1; + break; + case SND_SOC_DAIFMT_CBM_CFM: + audio3 |= WM8991_AIF_MSTR1; + break; + default: + return -EINVAL; + } + + audio1 &= ~WM8991_AIF_FMT_MASK; + + /* interface format */ + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + audio1 |= WM8991_AIF_TMF_I2S; + audio1 &= ~WM8991_AIF_LRCLK_INV; + break; + case SND_SOC_DAIFMT_RIGHT_J: + audio1 |= WM8991_AIF_TMF_RIGHTJ; + audio1 &= ~WM8991_AIF_LRCLK_INV; + break; + case SND_SOC_DAIFMT_LEFT_J: + audio1 |= WM8991_AIF_TMF_LEFTJ; + audio1 &= ~WM8991_AIF_LRCLK_INV; + break; + case SND_SOC_DAIFMT_DSP_A: + audio1 |= WM8991_AIF_TMF_DSP; + audio1 &= ~WM8991_AIF_LRCLK_INV; + break; + case SND_SOC_DAIFMT_DSP_B: + audio1 |= WM8991_AIF_TMF_DSP | WM8991_AIF_LRCLK_INV; + break; + default: + return -EINVAL; + } + + wm8991_write(codec, WM8991_AUDIO_INTERFACE_1, audio1); + wm8991_write(codec, WM8991_AUDIO_INTERFACE_3, audio3); + return 0; +} + +static int wm8991_set_dai_clkdiv(struct snd_soc_dai *codec_dai, + int div_id, int div) +{ + struct snd_soc_codec *codec = codec_dai->codec; + u16 reg; + + switch (div_id) { + case WM8991_MCLK_DIV: + reg = wm8991_read_reg_cache(codec, WM8991_CLOCKING_2) & + ~WM8991_MCLK_DIV_MASK; + wm8991_write(codec, WM8991_CLOCKING_2, reg | div); + break; + case WM8991_DACCLK_DIV: + reg = wm8991_read_reg_cache(codec, WM8991_CLOCKING_2) & + ~WM8991_DAC_CLKDIV_MASK; + wm8991_write(codec, WM8991_CLOCKING_2, reg | div); + break; + case WM8991_ADCCLK_DIV: + reg = wm8991_read_reg_cache(codec, WM8991_CLOCKING_2) & + ~WM8991_ADC_CLKDIV_MASK; + wm8991_write(codec, WM8991_CLOCKING_2, reg | div); + break; + case WM8991_BCLK_DIV: + reg = wm8991_read_reg_cache(codec, WM8991_CLOCKING_1) & + ~WM8991_BCLK_DIV_MASK; + wm8991_write(codec, WM8991_CLOCKING_1, reg | div); + break; + default: + return -EINVAL; + } + + return 0; +} + +/* + * Set PCM DAI bit size and sample rate. + */ +static int wm8991_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->codec; + u16 audio1 = wm8991_read_reg_cache(codec, WM8991_AUDIO_INTERFACE_1); + + audio1 &= ~WM8991_AIF_WL_MASK; + /* bit size */ + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + break; + case SNDRV_PCM_FORMAT_S20_3LE: + audio1 |= WM8991_AIF_WL_20BITS; + break; + case SNDRV_PCM_FORMAT_S24_LE: + audio1 |= WM8991_AIF_WL_24BITS; + break; + case SNDRV_PCM_FORMAT_S32_LE: + audio1 |= WM8991_AIF_WL_32BITS; + break; + } + + wm8991_write(codec, WM8991_AUDIO_INTERFACE_1, audio1); + return 0; +} + +static int wm8991_mute(struct snd_soc_dai *dai, int mute) +{ + return 0; +} + +static int wm8991_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level) +{ + return 0; +} + +#define WM8991_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ + SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \ + SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000) + +#define WM8991_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ + SNDRV_PCM_FMTBIT_S24_LE) + +/* + * The WM8991 supports 2 different and mutually exclusive DAI + * configurations. + * + * 1. ADC/DAC on Primary Interface + * 2. ADC on Primary Interface/DAC on secondary + */ +struct snd_soc_dai wm8991_dai = { +/* ADC/DAC on primary */ + .name = "WM8991 ADC/DAC Primary", + .id = 1, + .playback = { + .stream_name = "Playback", + .channels_min = 1, + .channels_max = 2, + .rates = WM8991_RATES, + .formats = WM8991_FORMATS,}, + .capture = { + .stream_name = "Capture", + .channels_min = 1, + .channels_max = 2, + .rates = WM8991_RATES, + .formats = WM8991_FORMATS,}, + .ops = { + .hw_params = wm8991_hw_params, + .digital_mute = wm8991_mute, + .set_fmt = wm8991_set_dai_fmt, + .set_clkdiv = wm8991_set_dai_clkdiv, + .set_pll = wm8991_set_dai_pll, + .set_sysclk = wm8991_set_dai_sysclk, + }, +}; +EXPORT_SYMBOL_GPL(wm8991_dai); + +static int wm8991_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + + /* we only need to suspend if we are a valid card */ + if (!codec->card) + return 0; + + wm8991_set_bias_level(codec, SND_SOC_BIAS_OFF); + return 0; +} + +static int wm8991_resume(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + int i; + u8 data[2]; + u16 *cache = codec->reg_cache; + + /* we only need to resume if we are a valid card */ + if (!codec->card) + return 0; + + /* Sync reg_cache with the hardware */ + for (i = 0; i < ARRAY_SIZE(wm8991_reg); i++) { + if (i + 1 == WM8991_RESET) + continue; + data[0] = ((i + 1) << 1) | ((cache[i] >> 8) & 0x0001); + data[1] = cache[i] & 0x00ff; + codec->hw_write(codec->control_data, data, 2); + } + + wm8991_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + return 0; +} + +/* + * initialise the WM8991 driver + * register the mixer and dsp interfaces with the kernel + */ +static int wm8991_init(struct snd_soc_device *socdev) +{ + struct snd_soc_codec *codec = socdev->codec; + u16 reg; + int ret = 0; + + codec->name = "WM8991"; + codec->owner = THIS_MODULE; + codec->read = wm8991_read_reg_cache; + codec->write = wm8991_write; + codec->set_bias_level = wm8991_set_bias_level; + codec->dai = &wm8991_dai; + codec->num_dai = 2; + codec->reg_cache_size = ARRAY_SIZE(wm8991_reg); + codec->reg_cache = kmemdup(wm8991_reg, sizeof(wm8991_reg), GFP_KERNEL); + + if (codec->reg_cache == NULL) + return -ENOMEM; + + wm8991_reset(codec); + + /* register pcms */ + ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); + if (ret < 0) { + printk(KERN_ERR "wm8991: failed to create pcms\n"); + goto pcm_err; + } + + /* charge output caps */ + wm8991_set_bias_level(codec, SNDRV_CTL_POWER_D2); + codec->bias_level = SND_SOC_BIAS_STANDBY; + + reg = wm8991_read_reg_cache(codec, WM8991_AUDIO_INTERFACE_4); + wm8991_write(codec, WM8991_AUDIO_INTERFACE_4, reg | WM8991_ALRCGPIO1); + + reg = wm8991_read_reg_cache(codec, WM8991_GPIO1_GPIO2) & + ~WM8991_GPIO1_SEL_MASK; + wm8991_write(codec, WM8991_GPIO1_GPIO2, reg | 1); + + reg = wm8991_read_reg_cache(codec, WM8991_POWER_MANAGEMENT_1); + wm8991_write(codec, WM8991_POWER_MANAGEMENT_1, reg | WM8991_VREF_ENA| + WM8991_VMID_MODE_MASK); + + reg = wm8991_read_reg_cache(codec, WM8991_POWER_MANAGEMENT_2); + wm8991_write(codec, WM8991_POWER_MANAGEMENT_2, reg | WM8991_OPCLK_ENA); + + wm8991_write(codec, WM8991_DAC_CTRL, 0); + wm8991_write(codec, WM8991_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8)); + wm8991_write(codec, WM8991_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8)); + + wm8991_add_controls(codec); + wm8991_add_widgets(codec); + ret = snd_soc_init_card(socdev); + if (ret < 0) { + printk(KERN_ERR "wm8991: failed to register card\n"); + goto card_err; + } + return ret; + +card_err: + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); +pcm_err: + kfree(codec->reg_cache); + return ret; +} + +/* If the i2c layer weren't so broken, we could pass this kind of data + around */ +static struct snd_soc_device *wm8991_socdev; + +#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) + +/* + * WM891 2 wire address is determined by GPIO5 + * state during powerup. + * low = 0x34 + * high = 0x36 + */ +static unsigned short normal_i2c[] = { 0, I2C_CLIENT_END }; + +/* Magic definition of all other variables and things */ +I2C_CLIENT_INSMOD; + +static struct i2c_driver wm8991_i2c_driver; +static struct i2c_client client_template; + +static int wm8991_codec_probe(struct i2c_adapter *adap, int addr, int kind) +{ + struct snd_soc_device *socdev = wm8991_socdev; + struct wm8991_setup_data *setup = socdev->codec_data; + struct snd_soc_codec *codec = socdev->codec; + struct i2c_client *i2c; + int ret; + + if (addr != setup->i2c_address) + return -ENODEV; + + client_template.adapter = adap; + client_template.addr = addr; + + i2c = kmemdup(&client_template, sizeof(client_template), GFP_KERNEL); + if (i2c == NULL) { + kfree(codec); + return -ENOMEM; + } + i2c_set_clientdata(i2c, codec); + codec->control_data = i2c; + + ret = i2c_attach_client(i2c); + if (ret < 0) { + pr_err("failed to attach codec at addr %x\n", addr); + goto err; + } + + ret = wm8991_init(socdev); + if (ret < 0) { + pr_err("failed to initialise WM8991\n"); + goto err; + } + return ret; + +err: + kfree(codec); + kfree(i2c); + return ret; +} + +static int wm8991_i2c_detach(struct i2c_client *client) +{ + struct snd_soc_codec *codec = i2c_get_clientdata(client); + i2c_detach_client(client); + kfree(codec->reg_cache); + kfree(client); + return 0; +} + +static int wm8991_i2c_attach(struct i2c_adapter *adap) +{ + return i2c_probe(adap, &addr_data, wm8991_codec_probe); +} + +/* corgi i2c codec control layer */ +static struct i2c_driver wm8991_i2c_driver = { + .driver = { + .name = "WM8991 I2C Codec", + .owner = THIS_MODULE, + }, + .attach_adapter = wm8991_i2c_attach, + .detach_client = wm8991_i2c_detach, + .command = NULL, +}; + +static struct i2c_client client_template = { + .name = "WM8991", + .driver = &wm8991_i2c_driver, +}; +#endif + +static int wm8991_probe(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct wm8991_setup_data *setup; + struct snd_soc_codec *codec; + struct wm8991_priv *wm8991; + int ret = 0; + + pr_info("WM8991 Audio Codec %s", WM8991_VERSION); + + setup = socdev->codec_data; + codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); + if (codec == NULL) + return -ENOMEM; + + wm8991 = kzalloc(sizeof(struct wm8991_priv), GFP_KERNEL); + if (wm8991 == NULL) { + kfree(codec); + return -ENOMEM; + } + + codec->private_data = wm8991; + socdev->codec = codec; + mutex_init(&codec->mutex); + INIT_LIST_HEAD(&codec->dapm_widgets); + INIT_LIST_HEAD(&codec->dapm_paths); + wm8991_socdev = socdev; + +#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) + if (setup->i2c_address) { + normal_i2c[0] = setup->i2c_address; + codec->hw_write = (hw_write_t)i2c_master_send; + ret = i2c_add_driver(&wm8991_i2c_driver); + if (ret != 0) + printk(KERN_ERR "can't add i2c driver"); + } +#else + /* Add other interfaces here */ +#endif + return ret; +} + +/* power down chip */ +static int wm8991_remove(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + + if (codec->control_data) + wm8991_set_bias_level(codec, SND_SOC_BIAS_OFF); + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); +#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) + i2c_del_driver(&wm8991_i2c_driver); +#endif + kfree(codec->private_data); + kfree(codec); + + return 0; +} + +struct snd_soc_codec_device soc_codec_dev_wm8991 = { + .probe = wm8991_probe, + .remove = wm8991_remove, + .suspend = wm8991_suspend, + .resume = wm8991_resume, +}; +EXPORT_SYMBOL_GPL(soc_codec_dev_wm8991); + +static int __init wm8991_modinit(void) +{ + return snd_soc_register_dai(&wm8991_dai); +} +module_init(wm8991_modinit); + +static void __exit wm8991_exit(void) +{ + snd_soc_unregister_dai(&wm8991_dai); +} +module_exit(wm8991_exit); + +MODULE_DESCRIPTION("ASoC WM8991 driver"); +MODULE_AUTHOR("Graeme Gregory"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/wm8991.h b/sound/soc/codecs/wm8991.h new file mode 100644 index 0000000..7d8be32 --- /dev/null +++ b/sound/soc/codecs/wm8991.h @@ -0,0 +1,902 @@ +/* + * wm8753.h -- audio driver for WM8753 + * + * Copyright 2007 Wolfson Microelectronics PLC. + * Author: Graeme Gregory + * graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef __WM8991REGISTERDEFS_H__ +#define __WM8991REGISTERDEFS_H__ + +/* + * Register values. + */ +#define WM8991_RESET 0x00 +#define WM8991_POWER_MANAGEMENT_1 0x01 +#define WM8991_POWER_MANAGEMENT_2 0x02 +#define WM8991_POWER_MANAGEMENT_3 0x03 +#define WM8991_AUDIO_INTERFACE_1 0x04 +#define WM8991_AUDIO_INTERFACE_2 0x05 +#define WM8991_CLOCKING_1 0x06 +#define WM8991_CLOCKING_2 0x07 +#define WM8991_AUDIO_INTERFACE_3 0x08 +#define WM8991_AUDIO_INTERFACE_4 0x09 +#define WM8991_DAC_CTRL 0x0A +#define WM8991_LEFT_DAC_DIGITAL_VOLUME 0x0B +#define WM8991_RIGHT_DAC_DIGITAL_VOLUME 0x0C +#define WM8991_DIGITAL_SIDE_TONE 0x0D +#define WM8991_ADC_CTRL 0x0E +#define WM8991_LEFT_ADC_DIGITAL_VOLUME 0x0F +#define WM8991_RIGHT_ADC_DIGITAL_VOLUME 0x10 +#define WM8991_GPIO_CTRL_1 0x12 +#define WM8991_GPIO1_GPIO2 0x13 +#define WM8991_GPIO3_GPIO4 0x14 +#define WM8991_GPIO5_GPIO6 0x15 +#define WM8991_GPIOCTRL_2 0x16 +#define WM8991_GPIO_POL 0x17 +#define WM8991_LEFT_LINE_INPUT_1_2_VOLUME 0x18 +#define WM8991_LEFT_LINE_INPUT_3_4_VOLUME 0x19 +#define WM8991_RIGHT_LINE_INPUT_1_2_VOLUME 0x1A +#define WM8991_RIGHT_LINE_INPUT_3_4_VOLUME 0x1B +#define WM8991_LEFT_OUTPUT_VOLUME 0x1C +#define WM8991_RIGHT_OUTPUT_VOLUME 0x1D +#define WM8991_LINE_OUTPUTS_VOLUME 0x1E +#define WM8991_OUT3_4_VOLUME 0x1F +#define WM8991_LEFT_OPGA_VOLUME 0x20 +#define WM8991_RIGHT_OPGA_VOLUME 0x21 +#define WM8991_SPEAKER_VOLUME 0x22 +#define WM8991_CLASSD1 0x23 +#define WM8991_CLASSD3 0x25 +#define WM8991_INPUT_MIXER1 0x27 +#define WM8991_INPUT_MIXER2 0x28 +#define WM8991_INPUT_MIXER3 0x29 +#define WM8991_INPUT_MIXER4 0x2A +#define WM8991_INPUT_MIXER5 0x2B +#define WM8991_INPUT_MIXER6 0x2C +#define WM8991_OUTPUT_MIXER1 0x2D +#define WM8991_OUTPUT_MIXER2 0x2E +#define WM8991_OUTPUT_MIXER3 0x2F +#define WM8991_OUTPUT_MIXER4 0x30 +#define WM8991_OUTPUT_MIXER5 0x31 +#define WM8991_OUTPUT_MIXER6 0x32 +#define WM8991_OUT3_4_MIXER 0x33 +#define WM8991_LINE_MIXER1 0x34 +#define WM8991_LINE_MIXER2 0x35 +#define WM8991_SPEAKER_MIXER 0x36 +#define WM8991_ADDITIONAL_CONTROL 0x37 +#define WM8991_ANTIPOP1 0x38 +#define WM8991_ANTIPOP2 0x39 +#define WM8991_MICBIAS 0x3A +#define WM8991_PLL1 0x3C +#define WM8991_PLL2 0x3D +#define WM8991_PLL3 0x3E +#define WM8991_INTDRIVBITS 0x3F + +#define WM8991_REGISTER_COUNT 60 +#define WM8991_MAX_REGISTER 0x3F + +/* + * Field Definitions. + */ + +/* + * R0 (0x00) - Reset + */ +#define WM8991_SW_RESET_CHIP_ID_MASK 0xFFFF /* SW_RESET_CHIP_ID - [15:0] */ + +/* + * R1 (0x01) - Power Management (1) + */ +#define WM8991_SPK_ENA 0x1000 /* SPK_ENA */ +#define WM8991_SPK_ENA_BIT 12 +#define WM8991_OUT3_ENA 0x0800 /* OUT3_ENA */ +#define WM8991_OUT3_ENA_BIT 11 +#define WM8991_OUT4_ENA 0x0400 /* OUT4_ENA */ +#define WM8991_OUT4_ENA_BIT 10 +#define WM8991_LOUT_ENA 0x0200 /* LOUT_ENA */ +#define WM8991_LOUT_ENA_BIT 9 +#define WM8991_ROUT_ENA 0x0100 /* ROUT_ENA */ +#define WM8991_ROUT_ENA_BIT 8 +#define WM8991_MICBIAS_ENA 0x0010 /* MICBIAS_ENA */ +#define WM8991_MICBIAS_ENA_BIT 4 +#define WM8991_VMID_MODE_MASK 0x0006 /* VMID_MODE - [2:1] */ +#define WM8991_VREF_ENA 0x0001 /* VREF_ENA */ +#define WM8991_VREF_ENA_BIT 0 + +/* + * R2 (0x02) - Power Management (2) + */ +#define WM8991_PLL_ENA 0x8000 /* PLL_ENA */ +#define WM8991_PLL_ENA_BIT 15 +#define WM8991_TSHUT_ENA 0x4000 /* TSHUT_ENA */ +#define WM8991_TSHUT_ENA_BIT 14 +#define WM8991_TSHUT_OPDIS 0x2000 /* TSHUT_OPDIS */ +#define WM8991_TSHUT_OPDIS_BIT 13 +#define WM8991_OPCLK_ENA 0x0800 /* OPCLK_ENA */ +#define WM8991_OPCLK_ENA_BIT 11 +#define WM8991_AINL_ENA 0x0200 /* AINL_ENA */ +#define WM8991_AINL_ENA_BIT 9 +#define WM8991_AINR_ENA 0x0100 /* AINR_ENA */ +#define WM8991_AINR_ENA_BIT 8 +#define WM8991_LIN34_ENA 0x0080 /* LIN34_ENA */ +#define WM8991_LIN34_ENA_BIT 7 +#define WM8991_LIN12_ENA 0x0040 /* LIN12_ENA */ +#define WM8991_LIN12_ENA_BIT 6 +#define WM8991_RIN34_ENA 0x0020 /* RIN34_ENA */ +#define WM8991_RIN34_ENA_BIT 5 +#define WM8991_RIN12_ENA 0x0010 /* RIN12_ENA */ +#define WM8991_RIN12_ENA_BIT 4 +#define WM8991_ADCL_ENA 0x0002 /* ADCL_ENA */ +#define WM8991_ADCL_ENA_BIT 1 +#define WM8991_ADCR_ENA 0x0001 /* ADCR_ENA */ +#define WM8991_ADCR_ENA_BIT 0 + +/* + * R3 (0x03) - Power Management (3) + */ +#define WM8991_LON_ENA 0x2000 /* LON_ENA */ +#define WM8991_LON_ENA_BIT 13 +#define WM8991_LOP_ENA 0x1000 /* LOP_ENA */ +#define WM8991_LOP_ENA_BIT 12 +#define WM8991_RON_ENA 0x0800 /* RON_ENA */ +#define WM8991_RON_ENA_BIT 11 +#define WM8991_ROP_ENA 0x0400 /* ROP_ENA */ +#define WM8991_ROP_ENA_BIT 10 +#define WM8991_LOPGA_ENA 0x0080 /* LOPGA_ENA */ +#define WM8991_LOPGA_ENA_BIT 7 +#define WM8991_ROPGA_ENA 0x0040 /* ROPGA_ENA */ +#define WM8991_ROPGA_ENA_BIT 6 +#define WM8991_LOMIX_ENA 0x0020 /* LOMIX_ENA */ +#define WM8991_LOMIX_ENA_BIT 5 +#define WM8991_ROMIX_ENA 0x0010 /* ROMIX_ENA */ +#define WM8991_ROMIX_ENA_BIT 4 +#define WM8991_DACL_ENA 0x0002 /* DACL_ENA */ +#define WM8991_DACL_ENA_BIT 1 +#define WM8991_DACR_ENA 0x0001 /* DACR_ENA */ +#define WM8991_DACR_ENA_BIT 0 + +/* + * R4 (0x04) - Audio Interface (1) + */ +#define WM8991_AIFADCL_SRC 0x8000 /* AIFADCL_SRC */ +#define WM8991_AIFADCR_SRC 0x4000 /* AIFADCR_SRC */ +#define WM8991_AIFADC_TDM 0x2000 /* AIFADC_TDM */ +#define WM8991_AIFADC_TDM_CHAN 0x1000 /* AIFADC_TDM_CHAN */ +#define WM8991_AIF_BCLK_INV 0x0100 /* AIF_BCLK_INV */ +#define WM8991_AIF_LRCLK_INV 0x0080 /* AIF_LRCLK_INV */ +#define WM8991_AIF_WL_MASK 0x0060 /* AIF_WL - [6:5] */ +#define WM8991_AIF_WL_16BITS (0 << 5) +#define WM8991_AIF_WL_20BITS (1 << 5) +#define WM8991_AIF_WL_24BITS (2 << 5) +#define WM8991_AIF_WL_32BITS (3 << 5) +#define WM8991_AIF_FMT_MASK 0x0018 /* AIF_FMT - [4:3] */ +#define WM8991_AIF_TMF_RIGHTJ (0 << 3) +#define WM8991_AIF_TMF_LEFTJ (1 << 3) +#define WM8991_AIF_TMF_I2S (2 << 3) +#define WM8991_AIF_TMF_DSP (3 << 3) + +/* + * R5 (0x05) - Audio Interface (2) + */ +#define WM8991_DACL_SRC 0x8000 /* DACL_SRC */ +#define WM8991_DACR_SRC 0x4000 /* DACR_SRC */ +#define WM8991_AIFDAC_TDM 0x2000 /* AIFDAC_TDM */ +#define WM8991_AIFDAC_TDM_CHAN 0x1000 /* AIFDAC_TDM_CHAN */ +#define WM8991_DAC_BOOST_MASK 0x0C00 /* DAC_BOOST - [11:10] */ +#define WM8991_DAC_COMP 0x0010 /* DAC_COMP */ +#define WM8991_DAC_COMPMODE 0x0008 /* DAC_COMPMODE */ +#define WM8991_ADC_COMP 0x0004 /* ADC_COMP */ +#define WM8991_ADC_COMPMODE 0x0002 /* ADC_COMPMODE */ +#define WM8991_LOOPBACK 0x0001 /* LOOPBACK */ + +/* + * R6 (0x06) - Clocking (1) + */ +#define WM8991_TOCLK_RATE 0x8000 /* TOCLK_RATE */ +#define WM8991_TOCLK_ENA 0x4000 /* TOCLK_ENA */ +#define WM8991_OPCLKDIV_MASK 0x1E00 /* OPCLKDIV - [12:9] */ +#define WM8991_DCLKDIV_MASK 0x01C0 /* DCLKDIV - [8:6] */ +#define WM8991_BCLK_DIV_MASK 0x001E /* BCLK_DIV - [4:1] */ +#define WM8991_BCLK_DIV_1 (0x0 << 1) +#define WM8991_BCLK_DIV_1_5 (0x1 << 1) +#define WM8991_BCLK_DIV_2 (0x2 << 1) +#define WM8991_BCLK_DIV_3 (0x3 << 1) +#define WM8991_BCLK_DIV_4 (0x4 << 1) +#define WM8991_BCLK_DIV_5_5 (0x5 << 1) +#define WM8991_BCLK_DIV_6 (0x6 << 1) +#define WM8991_BCLK_DIV_8 (0x7 << 1) +#define WM8991_BCLK_DIV_11 (0x8 << 1) +#define WM8991_BCLK_DIV_12 (0x9 << 1) +#define WM8991_BCLK_DIV_16 (0xA << 1) +#define WM8991_BCLK_DIV_22 (0xB << 1) +#define WM8991_BCLK_DIV_24 (0xC << 1) +#define WM8991_BCLK_DIV_32 (0xD << 1) +#define WM8991_BCLK_DIV_44 (0xE << 1) +#define WM8991_BCLK_DIV_48 (0xF << 1) + +/* + * R7 (0x07) - Clocking (2) + */ +#define WM8991_MCLK_SRC 0x8000 /* MCLK_SRC */ +#define WM8991_SYSCLK_SRC 0x4000 /* SYSCLK_SRC */ +#define WM8991_CLK_FORCE 0x2000 /* CLK_FORCE */ +#define WM8991_MCLK_DIV_MASK 0x1800 /* MCLK_DIV - [12:11] */ +#define WM8991_MCLK_DIV_1 (0 << 11) +#define WM8991_MCLK_DIV_2 ( 2 << 11) +#define WM8991_MCLK_INV 0x0400 /* MCLK_INV */ +#define WM8991_ADC_CLKDIV_MASK 0x00E0 /* ADC_CLKDIV - [7:5] */ +#define WM8991_ADC_CLKDIV_1 (0 << 5) +#define WM8991_ADC_CLKDIV_1_5 (1 << 5) +#define WM8991_ADC_CLKDIV_2 (2 << 5) +#define WM8991_ADC_CLKDIV_3 (3 << 5) +#define WM8991_ADC_CLKDIV_4 (4 << 5) +#define WM8991_ADC_CLKDIV_5_5 (5 << 5) +#define WM8991_ADC_CLKDIV_6 (6 << 5) +#define WM8991_DAC_CLKDIV_MASK 0x001C /* DAC_CLKDIV - [4:2] */ +#define WM8991_DAC_CLKDIV_1 (0 << 2) +#define WM8991_DAC_CLKDIV_1_5 (1 << 2) +#define WM8991_DAC_CLKDIV_2 (2 << 2) +#define WM8991_DAC_CLKDIV_3 (3 << 2) +#define WM8991_DAC_CLKDIV_4 (4 << 2) +#define WM8991_DAC_CLKDIV_5_5 (5 << 2) +#define WM8991_DAC_CLKDIV_6 (6 << 2) + +/* + * R8 (0x08) - Audio Interface (3) + */ +#define WM8991_AIF_MSTR1 0x8000 /* AIF_MSTR1 */ +#define WM8991_AIF_MSTR2 0x4000 /* AIF_MSTR2 */ +#define WM8991_AIF_SEL 0x2000 /* AIF_SEL */ +#define WM8991_ADCLRC_DIR 0x0800 /* ADCLRC_DIR */ +#define WM8991_ADCLRC_RATE_MASK 0x07FF /* ADCLRC_RATE - [10:0] */ + +/* + * R9 (0x09) - Audio Interface (4) + */ +#define WM8991_ALRCGPIO1 0x8000 /* ALRCGPIO1 */ +#define WM8991_ALRCBGPIO6 0x4000 /* ALRCBGPIO6 */ +#define WM8991_AIF_TRIS 0x2000 /* AIF_TRIS */ +#define WM8991_DACLRC_DIR 0x0800 /* DACLRC_DIR */ +#define WM8991_DACLRC_RATE_MASK 0x07FF /* DACLRC_RATE - [10:0] */ + +/* + * R10 (0x0A) - DAC CTRL + */ +#define WM8991_AIF_LRCLKRATE 0x0400 /* AIF_LRCLKRATE */ +#define WM8991_DAC_MONO 0x0200 /* DAC_MONO */ +#define WM8991_DAC_SB_FILT 0x0100 /* DAC_SB_FILT */ +#define WM8991_DAC_MUTERATE 0x0080 /* DAC_MUTERATE */ +#define WM8991_DAC_MUTEMODE 0x0040 /* DAC_MUTEMODE */ +#define WM8991_DEEMP_MASK 0x0030 /* DEEMP - [5:4] */ +#define WM8991_DAC_MUTE 0x0004 /* DAC_MUTE */ +#define WM8991_DACL_DATINV 0x0002 /* DACL_DATINV */ +#define WM8991_DACR_DATINV 0x0001 /* DACR_DATINV */ + +/* + * R11 (0x0B) - Left DAC Digital Volume + */ +#define WM8991_DAC_VU 0x0100 /* DAC_VU */ +#define WM8991_DACL_VOL_MASK 0x00FF /* DACL_VOL - [7:0] */ +#define WM8991_DACL_VOL_SHIFT 0 +/* + * R12 (0x0C) - Right DAC Digital Volume + */ +#define WM8991_DAC_VU 0x0100 /* DAC_VU */ +#define WM8991_DACR_VOL_MASK 0x00FF /* DACR_VOL - [7:0] */ +#define WM8991_DACR_VOL_SHIFT 0 +/* + * R13 (0x0D) - Digital Side Tone + */ +#define WM8991_ADCL_DAC_SVOL_MASK 0x0F /* ADCL_DAC_SVOL - [12:9] */ +#define WM8991_ADCL_DAC_SVOL_SHIFT 9 +#define WM8991_ADCR_DAC_SVOL_MASK 0x0F /* ADCR_DAC_SVOL - [8:5] */ +#define WM8991_ADCR_DAC_SVOL_SHIFT 5 +#define WM8991_ADC_TO_DACL_MASK 0x03 /* ADC_TO_DACL - [3:2] */ +#define WM8991_ADC_TO_DACL_SHIFT 2 +#define WM8991_ADC_TO_DACR_MASK 0x03 /* ADC_TO_DACR - [1:0] */ +#define WM8991_ADC_TO_DACR_SHIFT 0 + +/* + * R14 (0x0E) - ADC CTRL + */ +#define WM8991_ADC_HPF_ENA 0x0100 /* ADC_HPF_ENA */ +#define WM8991_ADC_HPF_ENA_BIT 8 +#define WM8991_ADC_HPF_CUT_MASK 0x03 /* ADC_HPF_CUT - [6:5] */ +#define WM8991_ADC_HPF_CUT_SHIFT 5 +#define WM8991_ADCL_DATINV 0x0002 /* ADCL_DATINV */ +#define WM8991_ADCL_DATINV_BIT 1 +#define WM8991_ADCR_DATINV 0x0001 /* ADCR_DATINV */ +#define WM8991_ADCR_DATINV_BIT 0 + +/* + * R15 (0x0F) - Left ADC Digital Volume + */ +#define WM8991_ADC_VU 0x0100 /* ADC_VU */ +#define WM8991_ADCL_VOL_MASK 0x00FF /* ADCL_VOL - [7:0] */ +#define WM8991_ADCL_VOL_SHIFT 0 + +/* + * R16 (0x10) - Right ADC Digital Volume + */ +#define WM8991_ADC_VU 0x0100 /* ADC_VU */ +#define WM8991_ADCR_VOL_MASK 0x00FF /* ADCR_VOL - [7:0] */ +#define WM8991_ADCR_VOL_SHIFT 0 + +/* + * R18 (0x12) - GPIO CTRL 1 + */ +#define WM8991_IRQ 0x1000 /* IRQ */ +#define WM8991_TEMPOK 0x0800 /* TEMPOK */ +#define WM8991_MICSHRT 0x0400 /* MICSHRT */ +#define WM8991_MICDET 0x0200 /* MICDET */ +#define WM8991_PLL_LCK 0x0100 /* PLL_LCK */ +#define WM8991_GPI8_STATUS 0x0080 /* GPI8_STATUS */ +#define WM8991_GPI7_STATUS 0x0040 /* GPI7_STATUS */ +#define WM8991_GPIO6_STATUS 0x0020 /* GPIO6_STATUS */ +#define WM8991_GPIO5_STATUS 0x0010 /* GPIO5_STATUS */ +#define WM8991_GPIO4_STATUS 0x0008 /* GPIO4_STATUS */ +#define WM8991_GPIO3_STATUS 0x0004 /* GPIO3_STATUS */ +#define WM8991_GPIO2_STATUS 0x0002 /* GPIO2_STATUS */ +#define WM8991_GPIO1_STATUS 0x0001 /* GPIO1_STATUS */ + +/* + * R19 (0x13) - GPIO1 & GPIO2 + */ +#define WM8991_GPIO2_DEB_ENA 0x8000 /* GPIO2_DEB_ENA */ +#define WM8991_GPIO2_IRQ_ENA 0x4000 /* GPIO2_IRQ_ENA */ +#define WM8991_GPIO2_PU 0x2000 /* GPIO2_PU */ +#define WM8991_GPIO2_PD 0x1000 /* GPIO2_PD */ +#define WM8991_GPIO2_SEL_MASK 0x0F00 /* GPIO2_SEL - [11:8] */ +#define WM8991_GPIO1_DEB_ENA 0x0080 /* GPIO1_DEB_ENA */ +#define WM8991_GPIO1_IRQ_ENA 0x0040 /* GPIO1_IRQ_ENA */ +#define WM8991_GPIO1_PU 0x0020 /* GPIO1_PU */ +#define WM8991_GPIO1_PD 0x0010 /* GPIO1_PD */ +#define WM8991_GPIO1_SEL_MASK 0x000F /* GPIO1_SEL - [3:0] */ + +/* + * R20 (0x14) - GPIO3 & GPIO4 + */ +#define WM8991_GPIO4_DEB_ENA 0x8000 /* GPIO4_DEB_ENA */ +#define WM8991_GPIO4_IRQ_ENA 0x4000 /* GPIO4_IRQ_ENA */ +#define WM8991_GPIO4_PU 0x2000 /* GPIO4_PU */ +#define WM8991_GPIO4_PD 0x1000 /* GPIO4_PD */ +#define WM8991_GPIO4_SEL_MASK 0x0F00 /* GPIO4_SEL - [11:8] */ +#define WM8991_GPIO3_DEB_ENA 0x0080 /* GPIO3_DEB_ENA */ +#define WM8991_GPIO3_IRQ_ENA 0x0040 /* GPIO3_IRQ_ENA */ +#define WM8991_GPIO3_PU 0x0020 /* GPIO3_PU */ +#define WM8991_GPIO3_PD 0x0010 /* GPIO3_PD */ +#define WM8991_GPIO3_SEL_MASK 0x000F /* GPIO3_SEL - [3:0] */ + +/* + * R21 (0x15) - GPIO5 & GPIO6 + */ +#define WM8991_GPIO6_DEB_ENA 0x8000 /* GPIO6_DEB_ENA */ +#define WM8991_GPIO6_IRQ_ENA 0x4000 /* GPIO6_IRQ_ENA */ +#define WM8991_GPIO6_PU 0x2000 /* GPIO6_PU */ +#define WM8991_GPIO6_PD 0x1000 /* GPIO6_PD */ +#define WM8991_GPIO6_SEL_MASK 0x0F00 /* GPIO6_SEL - [11:8] */ +#define WM8991_GPIO5_DEB_ENA 0x0080 /* GPIO5_DEB_ENA */ +#define WM8991_GPIO5_IRQ_ENA 0x0040 /* GPIO5_IRQ_ENA */ +#define WM8991_GPIO5_PU 0x0020 /* GPIO5_PU */ +#define WM8991_GPIO5_PD 0x0010 /* GPIO5_PD */ +#define WM8991_GPIO5_SEL_MASK 0x000F /* GPIO5_SEL - [3:0] */ + +/* + * R22 (0x16) - GPIOCTRL 2 + */ +#define WM8991_RD_3W_ENA 0x8000 /* RD_3W_ENA */ +#define WM8991_MODE_3W4W 0x4000 /* MODE_3W4W */ +#define WM8991_TEMPOK_IRQ_ENA 0x0800 /* TEMPOK_IRQ_ENA */ +#define WM8991_MICSHRT_IRQ_ENA 0x0400 /* MICSHRT_IRQ_ENA */ +#define WM8991_MICDET_IRQ_ENA 0x0200 /* MICDET_IRQ_ENA */ +#define WM8991_PLL_LCK_IRQ_ENA 0x0100 /* PLL_LCK_IRQ_ENA */ +#define WM8991_GPI8_DEB_ENA 0x0080 /* GPI8_DEB_ENA */ +#define WM8991_GPI8_IRQ_ENA 0x0040 /* GPI8_IRQ_ENA */ +#define WM8991_GPI8_ENA 0x0010 /* GPI8_ENA */ +#define WM8991_GPI7_DEB_ENA 0x0008 /* GPI7_DEB_ENA */ +#define WM8991_GPI7_IRQ_ENA 0x0004 /* GPI7_IRQ_ENA */ +#define WM8991_GPI7_ENA 0x0001 /* GPI7_ENA */ + +/* + * R23 (0x17) - GPIO_POL + */ +#define WM8991_IRQ_INV 0x1000 /* IRQ_INV */ +#define WM8991_TEMPOK_POL 0x0800 /* TEMPOK_POL */ +#define WM8991_MICSHRT_POL 0x0400 /* MICSHRT_POL */ +#define WM8991_MICDET_POL 0x0200 /* MICDET_POL */ +#define WM8991_PLL_LCK_POL 0x0100 /* PLL_LCK_POL */ +#define WM8991_GPI8_POL 0x0080 /* GPI8_POL */ +#define WM8991_GPI7_POL 0x0040 /* GPI7_POL */ +#define WM8991_GPIO6_POL 0x0020 /* GPIO6_POL */ +#define WM8991_GPIO5_POL 0x0010 /* GPIO5_POL */ +#define WM8991_GPIO4_POL 0x0008 /* GPIO4_POL */ +#define WM8991_GPIO3_POL 0x0004 /* GPIO3_POL */ +#define WM8991_GPIO2_POL 0x0002 /* GPIO2_POL */ +#define WM8991_GPIO1_POL 0x0001 /* GPIO1_POL */ + +/* + * R24 (0x18) - Left Line Input 1&2 Volume + */ +#define WM8991_IPVU 0x0100 /* IPVU */ +#define WM8991_LI12MUTE 0x0080 /* LI12MUTE */ +#define WM8991_LI12MUTE_BIT 7 +#define WM8991_LI12ZC 0x0040 /* LI12ZC */ +#define WM8991_LI12ZC_BIT 6 +#define WM8991_LIN12VOL_MASK 0x001F /* LIN12VOL - [4:0] */ +#define WM8991_LIN12VOL_SHIFT 0 +/* + * R25 (0x19) - Left Line Input 3&4 Volume + */ +#define WM8991_IPVU 0x0100 /* IPVU */ +#define WM8991_LI34MUTE 0x0080 /* LI34MUTE */ +#define WM8991_LI34MUTE_BIT 7 +#define WM8991_LI34ZC 0x0040 /* LI34ZC */ +#define WM8991_LI34ZC_BIT 6 +#define WM8991_LIN34VOL_MASK 0x001F /* LIN34VOL - [4:0] */ +#define WM8991_LIN34VOL_SHIFT 0 + +/* + * R26 (0x1A) - Right Line Input 1&2 Volume + */ +#define WM8991_IPVU 0x0100 /* IPVU */ +#define WM8991_RI12MUTE 0x0080 /* RI12MUTE */ +#define WM8991_RI12MUTE_BIT 7 +#define WM8991_RI12ZC 0x0040 /* RI12ZC */ +#define WM8991_RI12ZC_BIT 6 +#define WM8991_RIN12VOL_MASK 0x001F /* RIN12VOL - [4:0] */ +#define WM8991_RIN12VOL_SHIFT 0 + +/* + * R27 (0x1B) - Right Line Input 3&4 Volume + */ +#define WM8991_IPVU 0x0100 /* IPVU */ +#define WM8991_RI34MUTE 0x0080 /* RI34MUTE */ +#define WM8991_RI34MUTE_BIT 7 +#define WM8991_RI34ZC 0x0040 /* RI34ZC */ +#define WM8991_RI34ZC_BIT 6 +#define WM8991_RIN34VOL_MASK 0x001F /* RIN34VOL - [4:0] */ +#define WM8991_RIN34VOL_SHIFT 0 + +/* + * R28 (0x1C) - Left Output Volume + */ +#define WM8991_OPVU 0x0100 /* OPVU */ +#define WM8991_LOZC 0x0080 /* LOZC */ +#define WM8991_LOZC_BIT 7 +#define WM8991_LOUTVOL_MASK 0x007F /* LOUTVOL - [6:0] */ +#define WM8991_LOUTVOL_SHIFT 0 +/* + * R29 (0x1D) - Right Output Volume + */ +#define WM8991_OPVU 0x0100 /* OPVU */ +#define WM8991_ROZC 0x0080 /* ROZC */ +#define WM8991_ROZC_BIT 7 +#define WM8991_ROUTVOL_MASK 0x007F /* ROUTVOL - [6:0] */ +#define WM8991_ROUTVOL_SHIFT 0 +/* + * R30 (0x1E) - Line Outputs Volume + */ +#define WM8991_LONMUTE 0x0040 /* LONMUTE */ +#define WM8991_LONMUTE_BIT 6 +#define WM8991_LOPMUTE 0x0020 /* LOPMUTE */ +#define WM8991_LOPMUTE_BIT 5 +#define WM8991_LOATTN 0x0010 /* LOATTN */ +#define WM8991_LOATTN_BIT 4 +#define WM8991_RONMUTE 0x0004 /* RONMUTE */ +#define WM8991_RONMUTE_BIT 2 +#define WM8991_ROPMUTE 0x0002 /* ROPMUTE */ +#define WM8991_ROPMUTE_BIT 1 +#define WM8991_ROATTN 0x0001 /* ROATTN */ +#define WM8991_ROATTN_BIT 0 + +/* + * R31 (0x1F) - Out3/4 Volume + */ +#define WM8991_OUT3MUTE 0x0020 /* OUT3MUTE */ +#define WM8991_OUT3MUTE_BIT 5 +#define WM8991_OUT3ATTN 0x0010 /* OUT3ATTN */ +#define WM8991_OUT3ATTN_BIT 4 +#define WM8991_OUT4MUTE 0x0002 /* OUT4MUTE */ +#define WM8991_OUT4MUTE_BIT 1 +#define WM8991_OUT4ATTN 0x0001 /* OUT4ATTN */ +#define WM8991_OUT4ATTN_BIT 0 + +/* + * R32 (0x20) - Left OPGA Volume + */ +#define WM8991_OPVU 0x0100 /* OPVU */ +#define WM8991_LOPGAZC 0x0080 /* LOPGAZC */ +#define WM8991_LOPGAZC_BIT 7 +#define WM8991_LOPGAVOL_MASK 0x007F /* LOPGAVOL - [6:0] */ +#define WM8991_LOPGAVOL_SHIFT 0 + +/* + * R33 (0x21) - Right OPGA Volume + */ +#define WM8991_OPVU 0x0100 /* OPVU */ +#define WM8991_ROPGAZC 0x0080 /* ROPGAZC */ +#define WM8991_ROPGAZC_BIT 7 +#define WM8991_ROPGAVOL_MASK 0x007F /* ROPGAVOL - [6:0] */ +#define WM8991_ROPGAVOL_SHIFT 0 +/* + * R34 (0x22) - Speaker Volume + */ +#define WM8991_SPKVOL_MASK 0x0003 /* SPKVOL - [1:0] */ +#define WM8991_SPKVOL_SHIFT 0 + +/* + * R35 (0x23) - ClassD1 + */ +#define WM8991_CDMODE 0x0100 /* CDMODE */ +#define WM8991_CDMODE_BIT 8 + +/* + * R37 (0x25) - ClassD3 + */ +#define WM8991_DCGAIN_MASK 0x0007 /* DCGAIN - [5:3] */ +#define WM8991_DCGAIN_SHIFT 3 +#define WM8991_ACGAIN_MASK 0x0007 /* ACGAIN - [2:0] */ +#define WM8991_ACGAIN_SHIFT 0 +/* + * R39 (0x27) - Input Mixer1 + */ +#define WM8991_AINLMODE_MASK 0x000C /* AINLMODE - [3:2] */ +#define WM8991_AINLMODE_SHIFT 2 +#define WM8991_AINRMODE_MASK 0x0003 /* AINRMODE - [1:0] */ +#define WM8991_AINRMODE_SHIFT 0 + +/* + * R40 (0x28) - Input Mixer2 + */ +#define WM8991_LMP4 0x0080 /* LMP4 */ +#define WM8991_LMP4_BIT 7 /* LMP4 */ +#define WM8991_LMN3 0x0040 /* LMN3 */ +#define WM8991_LMN3_BIT 6 /* LMN3 */ +#define WM8991_LMP2 0x0020 /* LMP2 */ +#define WM8991_LMP2_BIT 5 /* LMP2 */ +#define WM8991_LMN1 0x0010 /* LMN1 */ +#define WM8991_LMN1_BIT 4 /* LMN1 */ +#define WM8991_RMP4 0x0008 /* RMP4 */ +#define WM8991_RMP4_BIT 3 /* RMP4 */ +#define WM8991_RMN3 0x0004 /* RMN3 */ +#define WM8991_RMN3_BIT 2 /* RMN3 */ +#define WM8991_RMP2 0x0002 /* RMP2 */ +#define WM8991_RMP2_BIT 1 /* RMP2 */ +#define WM8991_RMN1 0x0001 /* RMN1 */ +#define WM8991_RMN1_BIT 0 /* RMN1 */ + +/* + * R41 (0x29) - Input Mixer3 + */ +#define WM8991_L34MNB 0x0100 /* L34MNB */ +#define WM8991_L34MNB_BIT 8 +#define WM8991_L34MNBST 0x0080 /* L34MNBST */ +#define WM8991_L34MNBST_BIT 7 +#define WM8991_L12MNB 0x0020 /* L12MNB */ +#define WM8991_L12MNB_BIT 5 +#define WM8991_L12MNBST 0x0010 /* L12MNBST */ +#define WM8991_L12MNBST_BIT 4 +#define WM8991_LDBVOL_MASK 0x0007 /* LDBVOL - [2:0] */ +#define WM8991_LDBVOL_SHIFT 0 + +/* + * R42 (0x2A) - Input Mixer4 + */ +#define WM8991_R34MNB 0x0100 /* R34MNB */ +#define WM8991_R34MNB_BIT 8 +#define WM8991_R34MNBST 0x0080 /* R34MNBST */ +#define WM8991_R34MNBST_BIT 7 +#define WM8991_R12MNB 0x0020 /* R12MNB */ +#define WM8991_R12MNB_BIT 5 +#define WM8991_R12MNBST 0x0010 /* R12MNBST */ +#define WM8991_R12MNBST_BIT 4 +#define WM8991_RDBVOL_MASK 0x0007 /* RDBVOL - [2:0] */ +#define WM8991_RDBVOL_SHIFT 0 + +/* + * R43 (0x2B) - Input Mixer5 + */ +#define WM8991_LI2BVOL_MASK 0x07 /* LI2BVOL - [8:6] */ +#define WM8991_LI2BVOL_SHIFT 6 +#define WM8991_LR4BVOL_MASK 0x07 /* LR4BVOL - [5:3] */ +#define WM8991_LR4BVOL_SHIFT 3 +#define WM8991_LL4BVOL_MASK 0x07 /* LL4BVOL - [2:0] */ +#define WM8991_LL4BVOL_SHIFT 0 + +/* + * R44 (0x2C) - Input Mixer6 + */ +#define WM8991_RI2BVOL_MASK 0x07 /* RI2BVOL - [8:6] */ +#define WM8991_RI2BVOL_SHIFT 6 +#define WM8991_RL4BVOL_MASK 0x07 /* RL4BVOL - [5:3] */ +#define WM8991_RL4BVOL_SHIFT 3 +#define WM8991_RR4BVOL_MASK 0x07 /* RR4BVOL - [2:0] */ +#define WM8991_RR4BVOL_SHIFT 0 + +/* + * R45 (0x2D) - Output Mixer1 + */ +#define WM8991_LRBLO 0x0080 /* LRBLO */ +#define WM8991_LRBLO_BIT 7 +#define WM8991_LLBLO 0x0040 /* LLBLO */ +#define WM8991_LLBLO_BIT 6 +#define WM8991_LRI3LO 0x0020 /* LRI3LO */ +#define WM8991_LRI3LO_BIT 5 +#define WM8991_LLI3LO 0x0010 /* LLI3LO */ +#define WM8991_LLI3LO_BIT 4 +#define WM8991_LR12LO 0x0008 /* LR12LO */ +#define WM8991_LR12LO_BIT 3 +#define WM8991_LL12LO 0x0004 /* LL12LO */ +#define WM8991_LL12LO_BIT 2 +#define WM8991_LDLO 0x0001 /* LDLO */ +#define WM8991_LDLO_BIT 0 + +/* + * R46 (0x2E) - Output Mixer2 + */ +#define WM8991_RLBRO 0x0080 /* RLBRO */ +#define WM8991_RLBRO_BIT 7 +#define WM8991_RRBRO 0x0040 /* RRBRO */ +#define WM8991_RRBRO_BIT 6 +#define WM8991_RLI3RO 0x0020 /* RLI3RO */ +#define WM8991_RLI3RO_BIT 5 +#define WM8991_RRI3RO 0x0010 /* RRI3RO */ +#define WM8991_RRI3RO_BIT 4 +#define WM8991_RL12RO 0x0008 /* RL12RO */ +#define WM8991_RL12RO_BIT 3 +#define WM8991_RR12RO 0x0004 /* RR12RO */ +#define WM8991_RR12RO_BIT 2 +#define WM8991_RDRO 0x0001 /* RDRO */ +#define WM8991_RDRO_BIT 0 + +/* + * R47 (0x2F) - Output Mixer3 + */ +#define WM8991_LLI3LOVOL_MASK 0x07 /* LLI3LOVOL - [8:6] */ +#define WM8991_LLI3LOVOL_SHIFT 6 +#define WM8991_LR12LOVOL_MASK 0x07 /* LR12LOVOL - [5:3] */ +#define WM8991_LR12LOVOL_SHIFT 3 +#define WM8991_LL12LOVOL_MASK 0x07 /* LL12LOVOL - [2:0] */ +#define WM8991_LL12LOVOL_SHIFT 0 + +/* + * R48 (0x30) - Output Mixer4 + */ +#define WM8991_RRI3ROVOL_MASK 0x07 /* RRI3ROVOL - [8:6] */ +#define WM8991_RRI3ROVOL_SHIFT 6 +#define WM8991_RL12ROVOL_MASK 0x07 /* RL12ROVOL - [5:3] */ +#define WM8991_RL12ROVOL_SHIFT 3 +#define WM8991_RR12ROVOL_MASK 0x07 /* RR12ROVOL - [2:0] */ +#define WM8991_RR12ROVOL_SHIFT 0 + +/* + * R49 (0x31) - Output Mixer5 + */ +#define WM8991_LRI3LOVOL_MASK 0x07 /* LRI3LOVOL - [8:6] */ +#define WM8991_LRI3LOVOL_SHIFT 6 +#define WM8991_LRBLOVOL_MASK 0x07 /* LRBLOVOL - [5:3] */ +#define WM8991_LRBLOVOL_SHIFT 3 +#define WM8991_LLBLOVOL_MASK 0x07 /* LLBLOVOL - [2:0] */ +#define WM8991_LLBLOVOL_SHIFT 0 + +/* + * R50 (0x32) - Output Mixer6 + */ +#define WM8991_RLI3ROVOL_MASK 0x07 /* RLI3ROVOL - [8:6] */ +#define WM8991_RLI3ROVOL_SHIFT 6 +#define WM8991_RLBROVOL_MASK 0x07 /* RLBROVOL - [5:3] */ +#define WM8991_RLBROVOL_SHIFT 3 +#define WM8991_RRBROVOL_MASK 0x07 /* RRBROVOL - [2:0] */ +#define WM8991_RRBROVOL_SHIFT 0 + +/* + * R51 (0x33) - Out3/4 Mixer + */ +#define WM8991_VSEL_MASK 0x0180 /* VSEL - [8:7] */ +#define WM8991_LI4O3 0x0020 /* LI4O3 */ +#define WM8991_LI4O3_BIT 5 +#define WM8991_LPGAO3 0x0010 /* LPGAO3 */ +#define WM8991_LPGAO3_BIT 4 +#define WM8991_RI4O4 0x0002 /* RI4O4 */ +#define WM8991_RI4O4_BIT 1 +#define WM8991_RPGAO4 0x0001 /* RPGAO4 */ +#define WM8991_RPGAO4_BIT 0 +/* + * R52 (0x34) - Line Mixer1 + */ +#define WM8991_LLOPGALON 0x0040 /* LLOPGALON */ +#define WM8991_LLOPGALON_BIT 6 +#define WM8991_LROPGALON 0x0020 /* LROPGALON */ +#define WM8991_LROPGALON_BIT 5 +#define WM8991_LOPLON 0x0010 /* LOPLON */ +#define WM8991_LOPLON_BIT 4 +#define WM8991_LR12LOP 0x0004 /* LR12LOP */ +#define WM8991_LR12LOP_BIT 2 +#define WM8991_LL12LOP 0x0002 /* LL12LOP */ +#define WM8991_LL12LOP_BIT 1 +#define WM8991_LLOPGALOP 0x0001 /* LLOPGALOP */ +#define WM8991_LLOPGALOP_BIT 0 +/* + * R53 (0x35) - Line Mixer2 + */ +#define WM8991_RROPGARON 0x0040 /* RROPGARON */ +#define WM8991_RROPGARON_BIT 6 +#define WM8991_RLOPGARON 0x0020 /* RLOPGARON */ +#define WM8991_RLOPGARON_BIT 5 +#define WM8991_ROPRON 0x0010 /* ROPRON */ +#define WM8991_ROPRON_BIT 4 +#define WM8991_RL12ROP 0x0004 /* RL12ROP */ +#define WM8991_RL12ROP_BIT 2 +#define WM8991_RR12ROP 0x0002 /* RR12ROP */ +#define WM8991_RR12ROP_BIT 1 +#define WM8991_RROPGAROP 0x0001 /* RROPGAROP */ +#define WM8991_RROPGAROP_BIT 0 + +/* + * R54 (0x36) - Speaker Mixer + */ +#define WM8991_LB2SPK 0x0080 /* LB2SPK */ +#define WM8991_LB2SPK_BIT 7 +#define WM8991_RB2SPK 0x0040 /* RB2SPK */ +#define WM8991_RB2SPK_BIT 6 +#define WM8991_LI2SPK 0x0020 /* LI2SPK */ +#define WM8991_LI2SPK_BIT 5 +#define WM8991_RI2SPK 0x0010 /* RI2SPK */ +#define WM8991_RI2SPK_BIT 4 +#define WM8991_LOPGASPK 0x0008 /* LOPGASPK */ +#define WM8991_LOPGASPK_BIT 3 +#define WM8991_ROPGASPK 0x0004 /* ROPGASPK */ +#define WM8991_ROPGASPK_BIT 2 +#define WM8991_LDSPK 0x0002 /* LDSPK */ +#define WM8991_LDSPK_BIT 1 +#define WM8991_RDSPK 0x0001 /* RDSPK */ +#define WM8991_RDSPK_BIT 0 + +/* + * R55 (0x37) - Additional Control + */ +#define WM8991_VROI 0x0001 /* VROI */ + +/* + * R56 (0x38) - AntiPOP1 + */ +#define WM8991_DIS_LLINE 0x0020 /* DIS_LLINE */ +#define WM8991_DIS_RLINE 0x0010 /* DIS_RLINE */ +#define WM8991_DIS_OUT3 0x0008 /* DIS_OUT3 */ +#define WM8991_DIS_OUT4 0x0004 /* DIS_OUT4 */ +#define WM8991_DIS_LOUT 0x0002 /* DIS_LOUT */ +#define WM8991_DIS_ROUT 0x0001 /* DIS_ROUT */ + +/* + * R57 (0x39) - AntiPOP2 + */ +#define WM8991_SOFTST 0x0040 /* SOFTST */ +#define WM8991_BUFIOEN 0x0008 /* BUFIOEN */ +#define WM8991_BUFDCOPEN 0x0004 /* BUFDCOPEN */ +#define WM8991_POBCTRL 0x0002 /* POBCTRL */ +#define WM8991_VMIDTOG 0x0001 /* VMIDTOG */ + +/* + * R58 (0x3A) - MICBIAS + */ +#define WM8991_MCDSCTH_MASK 0x00C0 /* MCDSCTH - [7:6] */ +#define WM8991_MCDTHR_MASK 0x0038 /* MCDTHR - [5:3] */ +#define WM8991_MCD 0x0004 /* MCD */ +#define WM8991_MBSEL 0x0001 /* MBSEL */ + +/* + * R60 (0x3C) - PLL1 + */ +#define WM8991_SDM 0x0080 /* SDM */ +#define WM8991_PRESCALE 0x0040 /* PRESCALE */ +#define WM8991_PLLN_MASK 0x000F /* PLLN - [3:0] */ + +/* + * R61 (0x3D) - PLL2 + */ +#define WM8991_PLLK1_MASK 0x00FF /* PLLK1 - [7:0] */ + +/* + * R62 (0x3E) - PLL3 + */ +#define WM8991_PLLK2_MASK 0x00FF /* PLLK2 - [7:0] */ + +/* + * R63 (0x3F) - Internal Driver Bits + */ +#define WM8991_INMIXL_PWR_BIT 0 +#define WM8991_AINLMUX_PWR_BIT 1 +#define WM8991_INMIXR_PWR_BIT 2 +#define WM8991_AINRMUX_PWR_BIT 3 + +/* + * Default values. + */ +#define WM8991_REGISTER_DEFAULTS \ +{ \ + /*0x8990,*/ /* R0 - Reset */ \ + 0x0000, /* R1 - Power Management (1) */ \ + 0x6000, /* R2 - Power Management (2) */ \ + 0x0000, /* R3 - Power Management (3) */ \ + 0x4050, /* R4 - Audio Interface (1) */ \ + 0x4000, /* R5 - Audio Interface (2) */ \ + 0x01C8, /* R6 - Clocking (1) */ \ + 0x0000, /* R7 - Clocking (2) */ \ + 0x0040, /* R8 - Audio Interface (3) */ \ + 0x0040, /* R9 - Audio Interface (4) */ \ + 0x0004, /* R10 - DAC CTRL */ \ + 0x00C0, /* R11 - Left DAC Digital Volume */ \ + 0x00C0, /* R12 - Right DAC Digital Volume */ \ + 0x0000, /* R13 - Digital Side Tone */ \ + 0x0100, /* R14 - ADC CTRL */ \ + 0x00C0, /* R15 - Left ADC Digital Volume */ \ + 0x00C0, /* R16 - Right ADC Digital Volume */ \ + 0x0000, /* R17 */ \ + 0x0000, /* R18 - GPIO CTRL 1 */ \ + 0x1000, /* R19 - GPIO1 & GPIO2 */ \ + 0x1010, /* R20 - GPIO3 & GPIO4 */ \ + 0x1010, /* R21 - GPIO5 & GPIO6 */ \ + 0x8000, /* R22 - GPIOCTRL 2 */ \ + 0x0800, /* R23 - GPIO_POL */ \ + 0x008B, /* R24 - Left Line Input 1&2 Volume */ \ + 0x008B, /* R25 - Left Line Input 3&4 Volume */ \ + 0x008B, /* R26 - Right Line Input 1&2 Volume */ \ + 0x008B, /* R27 - Right Line Input 3&4 Volume */ \ + 0x0000, /* R28 - Left Output Volume */ \ + 0x0000, /* R29 - Right Output Volume */ \ + 0x0066, /* R30 - Line Outputs Volume */ \ + 0x0022, /* R31 - Out3/4 Volume */ \ + 0x0079, /* R32 - Left OPGA Volume */ \ + 0x0079, /* R33 - Right OPGA Volume */ \ + 0x0003, /* R34 - Speaker Volume */ \ + 0x0003, /* R35 - ClassD1 */ \ + 0x0000, /* R36 */ \ + 0x0100, /* R37 - ClassD3 */ \ + 0x0000, /* R38 */ \ + 0x0000, /* R39 - Input Mixer1 */ \ + 0x0000, /* R40 - Input Mixer2 */ \ + 0x0000, /* R41 - Input Mixer3 */ \ + 0x0000, /* R42 - Input Mixer4 */ \ + 0x0000, /* R43 - Input Mixer5 */ \ + 0x0000, /* R44 - Input Mixer6 */ \ + 0x0000, /* R45 - Output Mixer1 */ \ + 0x0000, /* R46 - Output Mixer2 */ \ + 0x0000, /* R47 - Output Mixer3 */ \ + 0x0000, /* R48 - Output Mixer4 */ \ + 0x0000, /* R49 - Output Mixer5 */ \ + 0x0000, /* R50 - Output Mixer6 */ \ + 0x0180, /* R51 - Out3/4 Mixer */ \ + 0x0000, /* R52 - Line Mixer1 */ \ + 0x0000, /* R53 - Line Mixer2 */ \ + 0x0000, /* R54 - Speaker Mixer */ \ + 0x0000, /* R55 - Additional Control */ \ + 0x0000, /* R56 - AntiPOP1 */ \ + 0x0000, /* R57 - AntiPOP2 */ \ + 0x0000, /* R58 - MICBIAS */ \ + 0x0000, /* R59 */ \ + 0x0008, /* R60 - PLL1 */ \ + 0x0031, /* R61 - PLL2 */ \ + 0x0026, /* R62 - PLL3 */ \ +} + +struct wm8991_setup_data { + unsigned short i2c_address; +}; + +#define WM8991_MCLK_DIV 0 +#define WM8991_DACCLK_DIV 1 +#define WM8991_ADCCLK_DIV 2 +#define WM8991_BCLK_DIV 3 + +extern struct snd_soc_dai wm8991_dai; +extern struct snd_soc_codec_device soc_codec_dev_wm8991; + +#endif /* __WM8991REGISTERDEFS_H__ */ +/*------------------------------ END OF FILE ---------------------------------*/ diff --git a/sound/soc/codecs/wm9705.c b/sound/soc/codecs/wm9705.c new file mode 100644 index 0000000..cb26b6a --- /dev/null +++ b/sound/soc/codecs/wm9705.c @@ -0,0 +1,410 @@ +/* + * wm9705.c -- ALSA Soc WM9705 codec support + * + * Copyright 2008 Ian Molton + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; Version 2 of the License only. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * WM9705 register cache + */ +static const u16 wm9705_reg[] = { + 0x6150, 0x8000, 0x8000, 0x8000, /* 0x0 */ + 0x0000, 0x8000, 0x8008, 0x8008, /* 0x8 */ + 0x8808, 0x8808, 0x8808, 0x8808, /* 0x10 */ + 0x8808, 0x0000, 0x8000, 0x0000, /* 0x18 */ + 0x0000, 0x0000, 0x0000, 0x000f, /* 0x20 */ + 0x0605, 0x0000, 0xbb80, 0x0000, /* 0x28 */ + 0x0000, 0xbb80, 0x0000, 0x0000, /* 0x30 */ + 0x0000, 0x2000, 0x0000, 0x0000, /* 0x38 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 0x40 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 0x48 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 0x50 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 0x58 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 0x60 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 0x68 */ + 0x0000, 0x0808, 0x0000, 0x0006, /* 0x70 */ + 0x0000, 0x0000, 0x574d, 0x4c05, /* 0x78 */ +}; + +static const struct snd_kcontrol_new wm9705_snd_ac97_controls[] = { + SOC_DOUBLE("Master Playback Volume", AC97_MASTER, 8, 0, 31, 1), + SOC_SINGLE("Master Playback Switch", AC97_MASTER, 15, 1, 1), + SOC_DOUBLE("Headphone Playback Volume", AC97_HEADPHONE, 8, 0, 31, 1), + SOC_SINGLE("Headphone Playback Switch", AC97_HEADPHONE, 15, 1, 1), + SOC_DOUBLE("PCM Playback Volume", AC97_PCM, 8, 0, 31, 1), + SOC_SINGLE("PCM Playback Switch", AC97_PCM, 15, 1, 1), + SOC_SINGLE("Mono Playback Volume", AC97_MASTER_MONO, 0, 31, 1), + SOC_SINGLE("Mono Playback Switch", AC97_MASTER_MONO, 15, 1, 1), + SOC_SINGLE("PCBeep Playback Volume", AC97_PC_BEEP, 1, 15, 1), + SOC_SINGLE("Phone Playback Volume", AC97_PHONE, 0, 31, 1), + SOC_DOUBLE("Line Playback Volume", AC97_LINE, 8, 0, 31, 1), + SOC_DOUBLE("CD Playback Volume", AC97_CD, 8, 0, 31, 1), + SOC_SINGLE("Mic Playback Volume", AC97_MIC, 0, 31, 1), + SOC_SINGLE("Mic 20dB Boost Switch", AC97_MIC, 6, 1, 0), + SOC_DOUBLE("PCM Capture Volume", AC97_REC_GAIN, 8, 0, 15, 0), + SOC_SINGLE("PCM Capture Switch", AC97_REC_GAIN, 15, 1, 1), +}; + +static const char *wm9705_mic[] = {"Mic 1", "Mic 2"}; +static const char *wm9705_rec_sel[] = {"Mic", "CD", "NC", "NC", + "Line", "Stereo Mix", "Mono Mix", "Phone"}; + +static const struct soc_enum wm9705_enum_mic = + SOC_ENUM_SINGLE(AC97_GENERAL_PURPOSE, 8, 2, wm9705_mic); +static const struct soc_enum wm9705_enum_rec_l = + SOC_ENUM_SINGLE(AC97_REC_SEL, 8, 8, wm9705_rec_sel); +static const struct soc_enum wm9705_enum_rec_r = + SOC_ENUM_SINGLE(AC97_REC_SEL, 0, 8, wm9705_rec_sel); + +/* Headphone Mixer */ +static const struct snd_kcontrol_new wm9705_hp_mixer_controls[] = { + SOC_DAPM_SINGLE("PCBeep Playback Switch", AC97_PC_BEEP, 15, 1, 1), + SOC_DAPM_SINGLE("CD Playback Switch", AC97_CD, 15, 1, 1), + SOC_DAPM_SINGLE("Mic Playback Switch", AC97_MIC, 15, 1, 1), + SOC_DAPM_SINGLE("Phone Playback Switch", AC97_PHONE, 15, 1, 1), + SOC_DAPM_SINGLE("Line Playback Switch", AC97_LINE, 15, 1, 1), +}; + +/* Mic source */ +static const struct snd_kcontrol_new wm9705_mic_src_controls = + SOC_DAPM_ENUM("Route", wm9705_enum_mic); + +/* Capture source */ +static const struct snd_kcontrol_new wm9705_capture_selectl_controls = + SOC_DAPM_ENUM("Route", wm9705_enum_rec_l); +static const struct snd_kcontrol_new wm9705_capture_selectr_controls = + SOC_DAPM_ENUM("Route", wm9705_enum_rec_r); + +/* DAPM widgets */ +static const struct snd_soc_dapm_widget wm9705_dapm_widgets[] = { + SND_SOC_DAPM_MUX("Mic Source", SND_SOC_NOPM, 0, 0, + &wm9705_mic_src_controls), + SND_SOC_DAPM_MUX("Left Capture Source", SND_SOC_NOPM, 0, 0, + &wm9705_capture_selectl_controls), + SND_SOC_DAPM_MUX("Right Capture Source", SND_SOC_NOPM, 0, 0, + &wm9705_capture_selectr_controls), + SND_SOC_DAPM_DAC("Left DAC", "Left HiFi Playback", + SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_DAC("Right DAC", "Right HiFi Playback", + SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_MIXER_NAMED_CTL("HP Mixer", SND_SOC_NOPM, 0, 0, + &wm9705_hp_mixer_controls[0], + ARRAY_SIZE(wm9705_hp_mixer_controls)), + SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_ADC("Left ADC", "Left HiFi Capture", SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_ADC("Right ADC", "Right HiFi Capture", SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_PGA("Headphone PGA", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("Speaker PGA", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("Line PGA", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("Line out PGA", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("Mono PGA", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("Phone PGA", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("Mic PGA", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("PCBEEP PGA", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("CD PGA", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("ADC PGA", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_OUTPUT("HPOUTL"), + SND_SOC_DAPM_OUTPUT("HPOUTR"), + SND_SOC_DAPM_OUTPUT("LOUT"), + SND_SOC_DAPM_OUTPUT("ROUT"), + SND_SOC_DAPM_OUTPUT("MONOOUT"), + SND_SOC_DAPM_INPUT("PHONE"), + SND_SOC_DAPM_INPUT("LINEINL"), + SND_SOC_DAPM_INPUT("LINEINR"), + SND_SOC_DAPM_INPUT("CDINL"), + SND_SOC_DAPM_INPUT("CDINR"), + SND_SOC_DAPM_INPUT("PCBEEP"), + SND_SOC_DAPM_INPUT("MIC1"), + SND_SOC_DAPM_INPUT("MIC2"), +}; + +/* Audio map + * WM9705 has no switches to disable the route from the inputs to the HP mixer + * so in order to prevent active inputs from forcing the audio outputs to be + * constantly enabled, we use the mutes on those inputs to simulate such + * controls. + */ +static const struct snd_soc_dapm_route audio_map[] = { + /* HP mixer */ + {"HP Mixer", "PCBeep Playback Switch", "PCBEEP PGA"}, + {"HP Mixer", "CD Playback Switch", "CD PGA"}, + {"HP Mixer", "Mic Playback Switch", "Mic PGA"}, + {"HP Mixer", "Phone Playback Switch", "Phone PGA"}, + {"HP Mixer", "Line Playback Switch", "Line PGA"}, + {"HP Mixer", NULL, "Left DAC"}, + {"HP Mixer", NULL, "Right DAC"}, + + /* mono mixer */ + {"Mono Mixer", NULL, "HP Mixer"}, + + /* outputs */ + {"Headphone PGA", NULL, "HP Mixer"}, + {"HPOUTL", NULL, "Headphone PGA"}, + {"HPOUTR", NULL, "Headphone PGA"}, + {"Line out PGA", NULL, "HP Mixer"}, + {"LOUT", NULL, "Line out PGA"}, + {"ROUT", NULL, "Line out PGA"}, + {"Mono PGA", NULL, "Mono Mixer"}, + {"MONOOUT", NULL, "Mono PGA"}, + + /* inputs */ + {"CD PGA", NULL, "CDINL"}, + {"CD PGA", NULL, "CDINR"}, + {"Line PGA", NULL, "LINEINL"}, + {"Line PGA", NULL, "LINEINR"}, + {"Phone PGA", NULL, "PHONE"}, + {"Mic Source", "Mic 1", "MIC1"}, + {"Mic Source", "Mic 2", "MIC2"}, + {"Mic PGA", NULL, "Mic Source"}, + {"PCBEEP PGA", NULL, "PCBEEP"}, + + /* Left capture selector */ + {"Left Capture Source", "Mic", "Mic Source"}, + {"Left Capture Source", "CD", "CDINL"}, + {"Left Capture Source", "Line", "LINEINL"}, + {"Left Capture Source", "Stereo Mix", "HP Mixer"}, + {"Left Capture Source", "Mono Mix", "HP Mixer"}, + {"Left Capture Source", "Phone", "PHONE"}, + + /* Right capture source */ + {"Right Capture Source", "Mic", "Mic Source"}, + {"Right Capture Source", "CD", "CDINR"}, + {"Right Capture Source", "Line", "LINEINR"}, + {"Right Capture Source", "Stereo Mix", "HP Mixer"}, + {"Right Capture Source", "Mono Mix", "HP Mixer"}, + {"Right Capture Source", "Phone", "PHONE"}, + + {"ADC PGA", NULL, "Left Capture Source"}, + {"ADC PGA", NULL, "Right Capture Source"}, + + /* ADC's */ + {"Left ADC", NULL, "ADC PGA"}, + {"Right ADC", NULL, "ADC PGA"}, +}; + +static int wm9705_add_widgets(struct snd_soc_codec *codec) +{ + snd_soc_dapm_new_controls(codec, wm9705_dapm_widgets, + ARRAY_SIZE(wm9705_dapm_widgets)); + snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + snd_soc_dapm_new_widgets(codec); + + return 0; +} + +/* We use a register cache to enhance read performance. */ +static unsigned int ac97_read(struct snd_soc_codec *codec, unsigned int reg) +{ + u16 *cache = codec->reg_cache; + + switch (reg) { + case AC97_RESET: + case AC97_VENDOR_ID1: + case AC97_VENDOR_ID2: + return soc_ac97_ops.read(codec->ac97, reg); + default: + reg = reg >> 1; + + if (reg >= (ARRAY_SIZE(wm9705_reg))) + return -EIO; + + return cache[reg]; + } +} + +static int ac97_write(struct snd_soc_codec *codec, unsigned int reg, + unsigned int val) +{ + u16 *cache = codec->reg_cache; + + soc_ac97_ops.write(codec->ac97, reg, val); + reg = reg >> 1; + if (reg < (ARRAY_SIZE(wm9705_reg))) + cache[reg] = val; + + return 0; +} + +static int ac97_prepare(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->codec; + int reg; + u16 vra; + + vra = ac97_read(codec, AC97_EXTENDED_STATUS); + ac97_write(codec, AC97_EXTENDED_STATUS, vra | 0x1); + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + reg = AC97_PCM_FRONT_DAC_RATE; + else + reg = AC97_PCM_LR_ADC_RATE; + + return ac97_write(codec, reg, runtime->rate); +} + +#define WM9705_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | \ + SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \ + SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ + SNDRV_PCM_RATE_48000) + +struct snd_soc_dai wm9705_dai[] = { + { + .name = "AC97 HiFi", + .ac97_control = 1, + .playback = { + .stream_name = "HiFi Playback", + .channels_min = 1, + .channels_max = 2, + .rates = WM9705_AC97_RATES, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + }, + .capture = { + .stream_name = "HiFi Capture", + .channels_min = 1, + .channels_max = 2, + .rates = WM9705_AC97_RATES, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + }, + .ops = { + .prepare = ac97_prepare, + }, + }, + { + .name = "AC97 Aux", + .playback = { + .stream_name = "Aux Playback", + .channels_min = 1, + .channels_max = 1, + .rates = WM9705_AC97_RATES, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + }, + } +}; +EXPORT_SYMBOL_GPL(wm9705_dai); + +static int wm9705_reset(struct snd_soc_codec *codec) +{ + if (soc_ac97_ops.reset) { + soc_ac97_ops.reset(codec->ac97); + if (ac97_read(codec, 0) == wm9705_reg[0]) + return 0; /* Success */ + } + + return -EIO; +} + +static int wm9705_soc_probe(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec; + int ret = 0; + + printk(KERN_INFO "WM9705 SoC Audio Codec\n"); + + socdev->codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); + if (socdev->codec == NULL) + return -ENOMEM; + codec = socdev->codec; + mutex_init(&codec->mutex); + + codec->reg_cache = kmemdup(wm9705_reg, sizeof(wm9705_reg), GFP_KERNEL); + if (codec->reg_cache == NULL) { + ret = -ENOMEM; + goto cache_err; + } + codec->reg_cache_size = sizeof(wm9705_reg); + codec->reg_cache_step = 2; + + codec->name = "WM9705"; + codec->owner = THIS_MODULE; + codec->dai = wm9705_dai; + codec->num_dai = ARRAY_SIZE(wm9705_dai); + codec->write = ac97_write; + codec->read = ac97_read; + INIT_LIST_HEAD(&codec->dapm_widgets); + INIT_LIST_HEAD(&codec->dapm_paths); + + ret = snd_soc_new_ac97_codec(codec, &soc_ac97_ops, 0); + if (ret < 0) { + printk(KERN_ERR "wm9705: failed to register AC97 codec\n"); + goto codec_err; + } + + /* register pcms */ + ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); + if (ret < 0) + goto pcm_err; + + ret = wm9705_reset(codec); + if (ret) + goto reset_err; + + snd_soc_add_controls(codec, wm9705_snd_ac97_controls, + ARRAY_SIZE(wm9705_snd_ac97_controls)); + wm9705_add_widgets(codec); + + ret = snd_soc_init_card(socdev); + if (ret < 0) { + printk(KERN_ERR "wm9705: failed to register card\n"); + goto pcm_err; + } + + return 0; + +reset_err: + snd_soc_free_pcms(socdev); +pcm_err: + snd_soc_free_ac97_codec(codec); +codec_err: + kfree(codec->reg_cache); +cache_err: + kfree(socdev->codec); + socdev->codec = NULL; + return ret; +} + +static int wm9705_soc_remove(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->codec; + + if (codec == NULL) + return 0; + + snd_soc_dapm_free(socdev); + snd_soc_free_pcms(socdev); + snd_soc_free_ac97_codec(codec); + kfree(codec->reg_cache); + kfree(codec); + return 0; +} + +struct snd_soc_codec_device soc_codec_dev_wm9705 = { + .probe = wm9705_soc_probe, + .remove = wm9705_soc_remove, +}; +EXPORT_SYMBOL_GPL(soc_codec_dev_wm9705); + +MODULE_DESCRIPTION("ASoC WM9705 driver"); +MODULE_AUTHOR("Ian Molton"); +MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/codecs/wm9705.h b/sound/soc/codecs/wm9705.h new file mode 100644 index 0000000..d380f11 --- /dev/null +++ b/sound/soc/codecs/wm9705.h @@ -0,0 +1,14 @@ +/* + * wm9705.h -- WM9705 Soc Audio driver + */ + +#ifndef _WM9705_H +#define _WM9705_H + +#define WM9705_DAI_AC97_HIFI 0 +#define WM9705_DAI_AC97_AUX 1 + +extern struct snd_soc_dai wm9705_dai[2]; +extern struct snd_soc_codec_device soc_codec_dev_wm9705; + +#endif diff --git a/sound/soc/codecs/wm9712.c b/sound/soc/codecs/wm9712.c index af83d62..1b0ace0 100644 --- a/sound/soc/codecs/wm9712.c +++ b/sound/soc/codecs/wm9712.c @@ -154,21 +154,6 @@ SOC_SINGLE("Mic 2 Volume", AC97_MIC, 0, 31, 1), SOC_SINGLE("Mic 20dB Boost Switch", AC97_MIC, 7, 1, 0), }; -/* add non dapm controls */ -static int wm9712_add_controls(struct snd_soc_codec *codec) -{ - int err, i; - - for (i = 0; i < ARRAY_SIZE(wm9712_snd_ac97_controls); i++) { - err = snd_ctl_add(codec->card, - snd_soc_cnew(&wm9712_snd_ac97_controls[i], - codec, NULL)); - if (err < 0) - return err; - } - return 0; -} - /* We have to create a fake left and right HP mixers because * the codec only has a single control that is shared by both channels. * This makes it impossible to determine the audio path. @@ -698,7 +683,8 @@ static int wm9712_soc_probe(struct platform_device *pdev) ac97_write(codec, AC97_VIDEO, ac97_read(codec, AC97_VIDEO) | 0x3000); wm9712_set_bias_level(codec, SND_SOC_BIAS_STANDBY); - wm9712_add_controls(codec); + snd_soc_add_controls(codec, wm9712_snd_ac97_controls, + ARRAY_SIZE(wm9712_snd_ac97_controls)); wm9712_add_widgets(codec); ret = snd_soc_init_card(socdev); if (ret < 0) { diff --git a/sound/soc/codecs/wm9713.c b/sound/soc/codecs/wm9713.c index f3ca8aa..e636d8a 100644 --- a/sound/soc/codecs/wm9713.c +++ b/sound/soc/codecs/wm9713.c @@ -32,7 +32,6 @@ struct wm9713_priv { u32 pll_in; /* PLL input frequency */ - u32 pll_out; /* PLL output frequency */ }; static unsigned int ac97_read(struct snd_soc_codec *codec, @@ -190,21 +189,6 @@ SOC_SINGLE("3D Lower Cut-off Switch", AC97_REC_GAIN_MIC, 4, 1, 0), SOC_SINGLE("3D Depth", AC97_REC_GAIN_MIC, 0, 15, 1), }; -/* add non dapm controls */ -static int wm9713_add_controls(struct snd_soc_codec *codec) -{ - int err, i; - - for (i = 0; i < ARRAY_SIZE(wm9713_snd_ac97_controls); i++) { - err = snd_ctl_add(codec->card, - snd_soc_cnew(&wm9713_snd_ac97_controls[i], - codec, NULL)); - if (err < 0) - return err; - } - return 0; -} - /* We have to create a fake left and right HP mixers because * the codec only has a single control that is shared by both channels. * This makes it impossible to determine the audio path using the current @@ -738,13 +722,13 @@ static int wm9713_set_pll(struct snd_soc_codec *codec, struct _pll_div pll_div; /* turn PLL off ? */ - if (freq_in == 0 || freq_out == 0) { + if (freq_in == 0) { /* disable PLL power and select ext source */ reg = ac97_read(codec, AC97_HANDSET_RATE); ac97_write(codec, AC97_HANDSET_RATE, reg | 0x0080); reg = ac97_read(codec, AC97_EXTENDED_MID); ac97_write(codec, AC97_EXTENDED_MID, reg | 0x0200); - wm9713->pll_out = 0; + wm9713->pll_in = 0; return 0; } @@ -788,7 +772,6 @@ static int wm9713_set_pll(struct snd_soc_codec *codec, ac97_write(codec, AC97_EXTENDED_MID, reg & 0xfdff); reg = ac97_read(codec, AC97_HANDSET_RATE); ac97_write(codec, AC97_HANDSET_RATE, reg & 0xff7f); - wm9713->pll_out = freq_out; wm9713->pll_in = freq_in; /* wait 10ms AC97 link frames for the link to stabilise */ @@ -1164,8 +1147,8 @@ static int wm9713_soc_resume(struct platform_device *pdev) wm9713_set_bias_level(codec, SND_SOC_BIAS_STANDBY); /* do we need to re-start the PLL ? */ - if (wm9713->pll_out) - wm9713_set_pll(codec, 0, wm9713->pll_in, wm9713->pll_out); + if (wm9713->pll_in) + wm9713_set_pll(codec, 0, wm9713->pll_in, 0); /* only synchronise the codec if warm reset failed */ if (ret == 0) { @@ -1245,7 +1228,8 @@ static int wm9713_soc_probe(struct platform_device *pdev) reg = ac97_read(codec, AC97_CD) & 0x7fff; ac97_write(codec, AC97_CD, reg); - wm9713_add_controls(codec); + snd_soc_add_controls(codec, wm9713_snd_ac97_controls, + ARRAY_SIZE(wm9713_snd_ac97_controls)); wm9713_add_widgets(codec); ret = snd_soc_init_card(socdev); if (ret < 0) diff --git a/sound/soc/imx/Kconfig b/sound/soc/imx/Kconfig new file mode 100644 index 0000000..5ba891c --- /dev/null +++ b/sound/soc/imx/Kconfig @@ -0,0 +1,29 @@ +config SND_MXC_SOC + tristate "SoC Audio for the Freescale i.MX CPU" + depends on ARCH_MXC && SND + select SND_PCM + help + Say Y or M if you want to add support for codecs attached to + the MXC AC97, I2S or SSP interface. You will also need + to select the audio interfaces to support below. + +config SND_MXC_AC97 + tristate + select SND_AC97_CODEC + +config SND_MXC_SOC_AC97 + tristate + select AC97_BUS + +config SND_MXC_SOC_SSI + tristate + +config SND_SOC_MX31ADS_WM8753 + tristate "SoC Audio support for MX31 - WM8753" + depends on SND_MXC_SOC && ARCH_MX3 + select SND_MXC_SOC_SSI + select SND_SOC_WM8753 + help + Say Y if you want to add support for SoC audio on MX31ADS + with the WM8753. + diff --git a/sound/soc/imx/Makefile b/sound/soc/imx/Makefile new file mode 100644 index 0000000..a1474ef --- /dev/null +++ b/sound/soc/imx/Makefile @@ -0,0 +1,15 @@ +# i.MX Platform Support +snd-soc-imx21-objs := imx21-pcm.o +snd-soc-imx31-objs := imx31-pcm.o +snd-soc-imx-ac97-objs := imx-ac97.o +snd-soc-imx-ssi-objs := imx-ssi.o + +obj-$(CONFIG_SND_MXC_SOC) += snd-soc-imx31.o +obj-$(CONFIG_SND_MXC_SOC_AC97) += snd-soc-imx-ac97.o +obj-$(CONFIG_SND_MXC_SOC_SSI) += snd-soc-imx-ssi.o + +# i.MX Machine Support +snd-soc-mx31ads-wm8753-objs := mx31ads_wm8753.o +obj-$(CONFIG_SND_SOC_MX31ADS_WM8753) += snd-soc-mx31ads-wm8753.o +snd-soc-mx21ads-wm8731-objs := mx21ads_wm8731.o +obj-$(CONFIG_SND_SOC_MX21ADS_WM8731) += snd-soc-mx21ads-wm8731.o \ No newline at end of file diff --git a/sound/soc/imx/imx-ac97.c b/sound/soc/imx/imx-ac97.c new file mode 100644 index 0000000..2587180 --- /dev/null +++ b/sound/soc/imx/imx-ac97.c @@ -0,0 +1,222 @@ +/* + * imx-ssi.c -- SSI driver for Freescale IMX + * + * Copyright 2006 Wolfson Microelectronics PLC. + * Author: Liam Girdwood + * liam.girdwood@wolfsonmicro.com or linux@wolfsonmicro.com + * + * Based on mxc-alsa-mc13783 (C) 2006 Freescale. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Revision history + * 29th Aug 2006 Initial version. + * + */ + + +static imx_pcm_dma_params_t imx_ssi1_pcm_stereo_out = { + .name = "SSI1 PCM Stereo out", + .params = { + .bd_number = 1, + .transfer_type = emi_2_per, + .watermark_level = SDMA_TXFIFO_WATERMARK, + .word_size = TRANSFER_16BIT, // maybe add this in setup func + .per_address = SSI1_STX0, + .event_id = DMA_REQ_SSI1_TX1, + .peripheral_type = SSI, + }, +}; + +static imx_pcm_dma_params_t imx_ssi1_pcm_stereo_in = { + .name = "SSI1 PCM Stereo in", + .params = { + .bd_number = 1, + .transfer_type = per_2_emi, + .watermark_level = SDMA_RXFIFO_WATERMARK, + .word_size = TRANSFER_16BIT, // maybe add this in setup func + .per_address = SSI1_SRX0, + .event_id = DMA_REQ_SSI1_RX1, + .peripheral_type = SSI, + }, +}; + +static imx_pcm_dma_params_t imx_ssi2_pcm_stereo_out = { + .name = "SSI2 PCM Stereo out", + .params = { + .bd_number = 1, + .transfer_type = per_2_emi, + .watermark_level = SDMA_TXFIFO_WATERMARK, + .word_size = TRANSFER_16BIT, // maybe add this in setup func + .per_address = SSI2_STX0, + .event_id = DMA_REQ_SSI2_TX1, + .peripheral_type = SSI, + }, +}; + +static imx_pcm_dma_params_t imx_ssi2_pcm_stereo_in = { + .name = "SSI2 PCM Stereo in", + .params = { + .bd_number = 1, + .transfer_type = per_2_emi, + .watermark_level = SDMA_RXFIFO_WATERMARK, + .word_size = TRANSFER_16BIT, // maybe add this in setup func + .per_address = SSI2_SRX0, + .event_id = DMA_REQ_SSI2_RX1, + .peripheral_type = SSI, + }, +}; + +static unsigned short imx_ssi_ac97_read(struct snd_ac97 *ac97, unsigned short reg) +{ +} + +static void imx_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val) +{ +} + +static void imx_ssi_ac97_warm_reset(struct snd_ac97 *ac97) +{ +} + +static void imx_ssi_ac97_cold_reset(struct snd_ac97 *ac97) +{ +} + +struct snd_ac97_bus_ops soc_ac97_ops = { + .read = imx_ssi_ac97_read, + .write = imx_ssi_ac97_write, + .warm_reset = imx_ssi_ac97_warm_reset, + .reset = imx_ssi_ac97_cold_reset, +}; + + +static intimx_ssi1_ac97_probe(struct platform_device *pdev) +{ + int ret; + + + return ret; +} + +static void imx_ssi1_ac97_remove(struct platform_device *pdev) +{ + /* shutdown SSI */ + if(rtd->cpu_dai->id == 0) + SSI1_SCR &= ~SSI_SCR_SSIEN; + else + SSI2_SCR &= ~SSI_SCR_SSIEN; + } + +} + +static int imx_ssi1_ac97_prepare(struct snd_pcm_substream *substream) +{ + // set vra +} + +static int imx_ssi_startup(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + + if (!rtd->cpu_dai->active) { + + } + + return 0; +} + +static int imx_ssi1_trigger(struct snd_pcm_substream *substream, int cmd) +{ + + return ret; +} + +static void imx_ssi_shutdown(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + + +} + +#ifdef CONFIG_PM +static int imx_ssi_suspend(struct platform_device *dev, + struct snd_soc_cpu_dai *dai) +{ + if(!dai->active) + return 0; + + + return 0; +} + +static int imx_ssi_resume(struct platform_device *pdev, + struct snd_soc_cpu_dai *dai) +{ + if(!dai->active) + return 0; + + return 0; +} + +#else +#define imx_ssi_suspend NULL +#define imx_ssi_resume NULL +#endif + +#define IMX_AC97_RATES \ + (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ + SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\ + SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ + SNDRV_PCM_RATE_48000) + +struct snd_soc_cpu_dai imx_ssi_ac97_dai = { + .name = "imx-ac97-1", + .id = 0, + .type = SND_SOC_DAI_AC97, + .suspend = imx_ssi_suspend, + .resume = imx_ssi_resume, + .playback = { + .channels_min = 2, + .channels_max = 2, + .rates = IMX_AC97_RATES,}, + .capture = { + .channels_min = 2, + .channels_max = 2, + .rates = IMX_AC97_RATES,}, + .ops = { + .probe = imx_ac97_probe, + .remove = imx_ac97_shutdown, + .trigger = imx_ssi_trigger, + .prepare = imx_ssi_ac97_prepare,}, +}, +{ + .name = "imx-ac97-2", + .id = 1, + .type = SND_SOC_DAI_AC97, + .suspend = imx_ssi_suspend, + .resume = imx_ssi_resume, + .playback = { + .channels_min = 2, + .channels_max = 2, + .rates = IMX_AC97_RATES,}, + .capture = { + .channels_min = 2, + .channels_max = 2, + .rates = IMX_AC97_RATES,}, + .ops = { + .probe = imx_ac97_probe, + .remove = imx_ac97_shutdown, + .trigger = imx_ssi_trigger, + .prepare = imx_ssi_ac97_prepare,}, +}; + +EXPORT_SYMBOL_GPL(imx_ssi_ac97_dai); + +/* Module information */ +MODULE_AUTHOR("Liam Girdwood, liam.girdwood@wolfsonmicro.com, www.wolfsonmicro.com"); +MODULE_DESCRIPTION("i.MX ASoC AC97 driver"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/imx/imx-ssi.c b/sound/soc/imx/imx-ssi.c new file mode 100644 index 0000000..b9ff1de --- /dev/null +++ b/sound/soc/imx/imx-ssi.c @@ -0,0 +1,846 @@ +/* + * imx-ssi.c -- SSI driver for Freescale IMX + * + * Copyright 2006 Wolfson Microelectronics PLC. + * Author: Liam Girdwood + * liam.girdwood@wolfsonmicro.com or linux@wolfsonmicro.com + * + * Based on mxc-alsa-mc13783 (C) 2006 Freescale. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Revision history + * 29th Aug 2006 Initial version. + * + * TODO: + * Need to rework SSI register defs when new defs go into mainline. + * Add support for TDM and FIFO 1. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "imx-ssi.h" +#include "imx31-pcm.h" + +/* debug */ +#define IMX_SSI_DEBUG 0 +#if IMX_SSI_DEBUG +#define dbg(format, arg...) printk(format, ## arg) +#else +#define dbg(format, arg...) +#endif + +#define IMX_SSI_DUMP 0 +#if IMX_SSI_DUMP +#define SSI_DUMP() \ + printk("dump @ %s\n", __FUNCTION__); \ + printk("scr %x\n", SSI1_SCR); \ + printk("sisr %x\n", SSI1_SISR); \ + printk("stcr %x\n", SSI1_STCR); \ + printk("stccr %x\n", SSI1_STCCR); \ + printk("stfsr %x\n", SSI1_SFCSR); \ + printk("stmsk %x\n", SSI1_STMSK); \ + printk("sier %x\n", SSI1_SIER); +#else +#define SSI_DUMP() +#endif + +#define SSI1_PORT 0 +#define SSI2_PORT 1 + +static int ssi_active[2] = {0,0}; + +static struct mxc_pcm_dma_params imx_ssi1_pcm_stereo_out0 = { + .name = "SSI1 PCM Stereo out 0", + .params = { + .bd_number = 1, + .transfer_type = emi_2_per, + .watermark_level = SDMA_TXFIFO_WATERMARK, + .per_address = SSI1_BASE_ADDR, + .event_id = DMA_REQ_SSI1_TX1, + .peripheral_type = SSI, + }, +}; + +static struct mxc_pcm_dma_params imx_ssi1_pcm_stereo_out1 = { + .name = "SSI1 PCM Stereo out 1", + .params = { + .bd_number = 1, + .transfer_type = emi_2_per, + .watermark_level = SDMA_TXFIFO_WATERMARK, + .per_address = SSI1_BASE_ADDR + 0x4, + .event_id = DMA_REQ_SSI1_TX2, + .peripheral_type = SSI, + }, +}; + +static struct mxc_pcm_dma_params imx_ssi1_pcm_stereo_in0 = { + .name = "SSI1 PCM Stereo in 0", + .params = { + .bd_number = 1, + .transfer_type = per_2_emi, + .watermark_level = SDMA_RXFIFO_WATERMARK, + .per_address = SSI1_BASE_ADDR + 0x8, + .event_id = DMA_REQ_SSI1_RX1, + .peripheral_type = SSI, + }, +}; + +static struct mxc_pcm_dma_params imx_ssi1_pcm_stereo_in1 = { + .name = "SSI1 PCM Stereo in 1", + .params = { + .bd_number = 1, + .transfer_type = per_2_emi, + .watermark_level = SDMA_RXFIFO_WATERMARK, + .per_address = SSI1_BASE_ADDR + 0xc, + .event_id = DMA_REQ_SSI1_RX2, + .peripheral_type = SSI, + }, +}; + +static struct mxc_pcm_dma_params imx_ssi2_pcm_stereo_out0 = { + .name = "SSI2 PCM Stereo out 0", + .params = { + .bd_number = 1, + .transfer_type = per_2_emi, + .watermark_level = SDMA_TXFIFO_WATERMARK, + .per_address = SSI2_BASE_ADDR, + .event_id = DMA_REQ_SSI2_TX1, + .peripheral_type = SSI, + }, +}; + +static struct mxc_pcm_dma_params imx_ssi2_pcm_stereo_out1 = { + .name = "SSI2 PCM Stereo out 1", + .params = { + .bd_number = 1, + .transfer_type = per_2_emi, + .watermark_level = SDMA_TXFIFO_WATERMARK, + .per_address = SSI2_BASE_ADDR + 0x4, + .event_id = DMA_REQ_SSI2_TX2, + .peripheral_type = SSI, + }, +}; + +static struct mxc_pcm_dma_params imx_ssi2_pcm_stereo_in0 = { + .name = "SSI2 PCM Stereo in 0", + .params = { + .bd_number = 1, + .transfer_type = per_2_emi, + .watermark_level = SDMA_RXFIFO_WATERMARK, + .per_address = SSI2_BASE_ADDR + 0x8, + .event_id = DMA_REQ_SSI2_RX1, + .peripheral_type = SSI, + }, +}; + +static struct mxc_pcm_dma_params imx_ssi2_pcm_stereo_in1 = { + .name = "SSI2 PCM Stereo in 1", + .params = { + .bd_number = 1, + .transfer_type = per_2_emi, + .watermark_level = SDMA_RXFIFO_WATERMARK, + .per_address = SSI2_BASE_ADDR + 0xc, + .event_id = DMA_REQ_SSI2_RX2, + .peripheral_type = SSI, + }, +}; + +/* + * SSI system clock configuration. + * Should only be called when port is inactive (i.e. SSIEN = 0). + */ +static int imx_ssi_set_dai_sysclk(struct snd_soc_cpu_dai *cpu_dai, + int clk_id, unsigned int freq, int dir) +{ + u32 scr; + + if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2) + scr = SSI1_SCR; + else + scr = SSI2_SCR; + + if (scr & SSI_SCR_SSIEN) + return 0; + + switch (clk_id) { + case IMX_SSP_SYS_CLK: + if (dir == SND_SOC_CLOCK_OUT) + scr |= SSI_SCR_SYS_CLK_EN; + else + scr &= ~SSI_SCR_SYS_CLK_EN; + break; + default: + return -EINVAL; + } + + if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2) + SSI1_SCR = scr; + else + SSI2_SCR = scr; + + return 0; +} + +/* + * SSI Clock dividers + * Should only be called when port is inactive (i.e. SSIEN = 0). + */ +static int imx_ssi_set_dai_clkdiv(struct snd_soc_cpu_dai *cpu_dai, + int div_id, int div) +{ + u32 stccr, srccr; + + if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2) { + if (SSI1_SCR & SSI_SCR_SSIEN) + return 0; + + srccr = SSI1_STCCR; + stccr = SSI1_STCCR; + } else { + if (SSI2_SCR & SSI_SCR_SSIEN) + return 0; + + srccr = SSI2_STCCR; + stccr = SSI2_STCCR; + } + + switch (div_id) { + case IMX_SSI_TX_DIV_2: + stccr &= ~SSI_STCCR_DIV2; + stccr |= div; + break; + case IMX_SSI_TX_DIV_PSR: + stccr &= ~SSI_STCCR_PSR; + stccr |= div; + break; + case IMX_SSI_TX_DIV_PM: + stccr &= ~0xff; + stccr |= SSI_STCCR_PM(div); + break; + case IMX_SSI_RX_DIV_2: + stccr &= ~SSI_STCCR_DIV2; + stccr |= div; + break; + case IMX_SSI_RX_DIV_PSR: + stccr &= ~SSI_STCCR_PSR; + stccr |= div; + break; + case IMX_SSI_RX_DIV_PM: + stccr &= ~0xff; + stccr |= SSI_STCCR_PM(div); + break; + default: + return -EINVAL; + } + + if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2) { + SSI1_STCCR = stccr; + SSI1_SRCCR = srccr; + } else { + SSI2_STCCR = stccr; + SSI2_SRCCR = srccr; + } + return 0; +} + +/* + * SSI Network Mode or TDM slots configuration. + * Should only be called when port is inactive (i.e. SSIEN = 0). + */ +static int imx_ssi_set_dai_tdm_slot(struct snd_soc_cpu_dai *cpu_dai, + unsigned int mask, int slots) +{ + u32 stmsk, srmsk, stccr; + + if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2) { + if (SSI1_SCR & SSI_SCR_SSIEN) + return 0; + stccr = SSI1_STCCR; + } else { + if (SSI2_SCR & SSI_SCR_SSIEN) + return 0; + stccr = SSI2_STCCR; + } + + stmsk = srmsk = mask; + stccr &= ~SSI_STCCR_DC_MASK; + stccr |= SSI_STCCR_DC(slots - 1); + + if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2) { + SSI1_STMSK = stmsk; + SSI1_SRMSK = srmsk; + SSI1_SRCCR = SSI1_STCCR = stccr; + } else { + SSI2_STMSK = stmsk; + SSI2_SRMSK = srmsk; + SSI2_SRCCR = SSI2_STCCR = stccr; + } + + return 0; +} + +/* + * SSI DAI format configuration. + * Should only be called when port is inactive (i.e. SSIEN = 0). + * Note: We don't use the I2S modes but instead manually configure the + * SSI for I2S. + */ +static int imx_ssi_set_dai_fmt(struct snd_soc_cpu_dai *cpu_dai, + unsigned int fmt) +{ + u32 stcr = 0, srcr = 0, scr; + + if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2) + scr = SSI1_SCR & ~(SSI_SCR_SYN | SSI_SCR_NET); + else + scr = SSI2_SCR & ~(SSI_SCR_SYN | SSI_SCR_NET); + + if (scr & SSI_SCR_SSIEN) + return 0; + + /* DAI mode */ + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + /* data on rising edge of bclk, frame low 1clk before data */ + stcr |= SSI_STCR_TFSI | SSI_STCR_TEFS | SSI_STCR_TXBIT0; + srcr |= SSI_SRCR_RFSI | SSI_SRCR_REFS | SSI_SRCR_RXBIT0; + break; + case SND_SOC_DAIFMT_LEFT_J: + /* data on rising edge of bclk, frame high with data */ + stcr |= SSI_STCR_TXBIT0; + srcr |= SSI_SRCR_RXBIT0; + break; + case SND_SOC_DAIFMT_DSP_B: + /* data on rising edge of bclk, frame high with data */ + stcr |= SSI_STCR_TFSL; + srcr |= SSI_SRCR_RFSL; + break; + case SND_SOC_DAIFMT_DSP_A: + /* data on rising edge of bclk, frame high 1clk before data */ + stcr |= SSI_STCR_TFSL | SSI_STCR_TEFS; + srcr |= SSI_SRCR_RFSL | SSI_SRCR_REFS; + break; + } + + /* DAI clock inversion */ + switch(fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_IB_IF: + stcr |= SSI_STCR_TFSI; + stcr &= ~SSI_STCR_TSCKP; + srcr |= SSI_SRCR_RFSI; + srcr &= ~SSI_SRCR_RSCKP; + break; + case SND_SOC_DAIFMT_IB_NF: + stcr &= ~(SSI_STCR_TSCKP | SSI_STCR_TFSI); + srcr &= ~(SSI_SRCR_RSCKP | SSI_SRCR_RFSI); + break; + case SND_SOC_DAIFMT_NB_IF: + stcr |= SSI_STCR_TFSI | SSI_STCR_TSCKP; + srcr |= SSI_SRCR_RFSI | SSI_SRCR_RSCKP; + break; + case SND_SOC_DAIFMT_NB_NF: + stcr &= ~SSI_STCR_TFSI; + stcr |= SSI_STCR_TSCKP; + srcr &= ~SSI_SRCR_RFSI; + srcr |= SSI_SRCR_RSCKP; + break; + } + + /* DAI clock master masks */ + switch(fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBS_CFS: + stcr |= SSI_STCR_TFDIR | SSI_STCR_TXDIR; + srcr |= SSI_SRCR_RFDIR | SSI_SRCR_RXDIR; + break; + case SND_SOC_DAIFMT_CBM_CFS: + stcr |= SSI_STCR_TFDIR; + srcr |= SSI_SRCR_RFDIR; + break; + case SND_SOC_DAIFMT_CBS_CFM: + stcr |= SSI_STCR_TXDIR; + srcr |= SSI_SRCR_RXDIR; + break; + } + + /* async */ + if (fmt & SND_SOC_DAIFMT_ASYNC) + scr |= SSI_SCR_SYN; + + /* tdm - only for stereo atm */ + if (fmt & SND_SOC_DAIFMT_TDM) + scr |= SSI_SCR_NET; + + if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2) { + SSI1_STCR = stcr; + SSI1_SRCR = srcr; + SSI1_SCR = scr; + } else { + SSI2_STCR = stcr; + SSI2_SRCR = srcr; + SSI1_SCR = scr; + } + SSI_DUMP(); + return 0; +} + +static int imx_ssi_startup(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai; + + /* we cant really change any SSI values after SSI is enabled + * need to fix in software for max flexibility - lrg */ + if (cpu_dai->active) + return 0; + + /* reset the SSI port - Sect 45.4.4 */ + if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2) { + + if (ssi_active[SSI1_PORT]++) + return 0; + + SSI1_SCR = 0; + mxc_clks_enable(SSI1_BAUD); + + + /* BIG FAT WARNING + * SDMA FIFO watermark must == SSI FIFO watermark for + * best results. + */ + SSI1_SFCSR = SSI_SFCSR_RFWM1(SDMA_RXFIFO_WATERMARK) | + SSI_SFCSR_RFWM0(SDMA_RXFIFO_WATERMARK) | + SSI_SFCSR_TFWM1(SDMA_TXFIFO_WATERMARK) | + SSI_SFCSR_TFWM0(SDMA_TXFIFO_WATERMARK); + } else { + + if (ssi_active[SSI2_PORT]++) + return 0; + + SSI2_SCR = 0; + mxc_clks_enable(SSI2_BAUD); + + /* above warning applies here too */ + SSI2_SFCSR = SSI_SFCSR_RFWM1(SDMA_RXFIFO_WATERMARK) | + SSI_SFCSR_RFWM0(SDMA_RXFIFO_WATERMARK) | + SSI_SFCSR_TFWM1(SDMA_TXFIFO_WATERMARK) | + SSI_SFCSR_TFWM0(SDMA_TXFIFO_WATERMARK); + } + + SSI_DUMP(); + return 0; +} + +static int imx_ssi_hw_tx_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai; + u32 stccr, stcr, sier; + + if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2) { + stccr = SSI1_STCCR & ~SSI_STCCR_WL_MASK; + stcr = SSI1_STCR; + sier = SSI1_SIER; + } else { + stccr = SSI2_STCCR & ~SSI_STCCR_WL_MASK; + stcr = SSI2_STCR; + sier = SSI2_SIER; + } + + /* DAI data (word) size */ + switch(params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + stccr |= SSI_STCCR_WL(16); + break; + case SNDRV_PCM_FORMAT_S20_3LE: + stccr |= SSI_STCCR_WL(20); + break; + case SNDRV_PCM_FORMAT_S24_LE: + stccr |= SSI_STCCR_WL(24); + break; + } + + /* enable interrupts */ + if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2) + stcr |= SSI_STCR_TFEN0; + else + stcr |= SSI_STCR_TFEN1; + sier |= SSI_SIER_TDMAE; + + if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2) { + SSI1_STCR = stcr; + SSI1_STCCR = stccr; + SSI1_SIER = sier; + } else { + SSI2_STCR = stcr; + SSI2_STCCR = stccr; + SSI2_SIER = sier; + } + + return 0; +} + +static int imx_ssi_hw_rx_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai; + u32 srccr, srcr, sier; + + if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2) { + srccr = SSI1_SRCCR & ~SSI_SRCCR_WL_MASK; + srcr = SSI1_SRCR; + sier = SSI1_SIER; + } else { + srccr = SSI2_SRCCR & ~SSI_SRCCR_WL_MASK; + srcr = SSI2_SRCR; + sier = SSI2_SIER; + } + + /* DAI data (word) size */ + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + srccr |= SSI_SRCCR_WL(16); + break; + case SNDRV_PCM_FORMAT_S20_3LE: + srccr |= SSI_SRCCR_WL(20); + break; + case SNDRV_PCM_FORMAT_S24_LE: + srccr |= SSI_SRCCR_WL(24); + break; + } + + /* enable interrupts */ + if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2) + srcr |= SSI_SRCR_RFEN0; + else + srcr |= SSI_SRCR_RFEN1; + sier |= SSI_SIER_RDMAE; + + if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2) { + SSI1_SRCR = srcr; + SSI1_SRCCR = srccr; + SSI1_SIER = sier; + } else { + SSI2_SRCR = srcr; + SSI2_SRCCR = srccr; + SSI2_SIER = sier; + } + return 0; +} + +/* + * Should only be called when port is inactive (i.e. SSIEN = 0), + * although can be called multiple times by upper layers. + */ +static int imx_ssi_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai; + + /* Tx/Rx config */ + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + /* set up DMA params */ + switch (cpu_dai->id) { + case IMX_DAI_SSI0: + cpu_dai->dma_data = &imx_ssi1_pcm_stereo_out0; + break; + case IMX_DAI_SSI1: + cpu_dai->dma_data = &imx_ssi1_pcm_stereo_out1; + break; + case IMX_DAI_SSI2: + cpu_dai->dma_data = &imx_ssi2_pcm_stereo_out0; + break; + case IMX_DAI_SSI3: + cpu_dai->dma_data = &imx_ssi2_pcm_stereo_out1; + break; + } + + /* cant change any parameters when SSI is running */ + if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2) { + if (SSI1_SCR & SSI_SCR_SSIEN) + return 0; + } else { + if (SSI2_SCR & SSI_SCR_SSIEN) + return 0; + } + return imx_ssi_hw_tx_params(substream, params); + } else { + /* set up DMA params */ + switch (cpu_dai->id) { + case IMX_DAI_SSI0: + cpu_dai->dma_data = &imx_ssi1_pcm_stereo_in0; + break; + case IMX_DAI_SSI1: + cpu_dai->dma_data = &imx_ssi1_pcm_stereo_in1; + break; + case IMX_DAI_SSI2: + cpu_dai->dma_data = &imx_ssi2_pcm_stereo_in0; + break; + case IMX_DAI_SSI3: + cpu_dai->dma_data = &imx_ssi2_pcm_stereo_in1; + break; + } + + /* cant change any parameters when SSI is running */ + if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2) { + if (SSI1_SCR & SSI_SCR_SSIEN) + return 0; + } else { + if (SSI2_SCR & SSI_SCR_SSIEN) + return 0; + } + return imx_ssi_hw_rx_params(substream, params); + } +} + +static int imx_ssi_prepare(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai; + u32 scr; + + /* enable the SSI port, note that no other port config + * should happen after SSIEN is set */ + if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2) { + scr = SSI1_SCR; + SSI1_SCR = scr | SSI_SCR_SSIEN; + } else { + scr = SSI2_SCR; + SSI2_SCR = scr | SSI_SCR_SSIEN; + } + SSI_DUMP(); + return 0; +} + +static int imx_ssi_trigger(struct snd_pcm_substream *substream, int cmd) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai; + u32 scr; + + if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2) + scr = SSI1_SCR; + else + scr = SSI2_SCR; + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + case SNDRV_PCM_TRIGGER_RESUME: + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + scr |= SSI_SCR_TE; + else + scr |= SSI_SCR_RE; + break; + case SNDRV_PCM_TRIGGER_SUSPEND: + case SNDRV_PCM_TRIGGER_STOP: + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + scr &= ~SSI_SCR_TE; + else + scr &= ~SSI_SCR_RE; + break; + default: + return -EINVAL; + } + + if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI2) + SSI1_SCR = scr; + else + SSI2_SCR = scr; + + SSI_DUMP(); + return 0; +} + +static void imx_ssi_shutdown(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai; + + /* shutdown SSI if neither Tx or Rx is active */ + if (!cpu_dai->active) { + + if (cpu_dai->id == IMX_DAI_SSI0 || + cpu_dai->id == IMX_DAI_SSI2) { + + if (--ssi_active[SSI1_PORT] > 1) + return; + + SSI1_SCR = 0; + mxc_clks_disable(SSI1_BAUD); + } else { + if (--ssi_active[SSI2_PORT]) + return; + SSI2_SCR = 0; + mxc_clks_disable(SSI2_BAUD); + } + } +} + +#ifdef CONFIG_PM +static int imx_ssi_suspend(struct platform_device *dev, + struct snd_soc_cpu_dai *dai) +{ + if(!dai->active) + return 0; + + // do we need to disable any clocks + + return 0; +} + +static int imx_ssi_resume(struct platform_device *pdev, + struct snd_soc_cpu_dai *dai) +{ + if(!dai->active) + return 0; + + // do we need to enable any clocks + return 0; +} + +#else +#define imx_ssi_suspend NULL +#define imx_ssi_resume NULL +#endif + +#define IMX_SSI_RATES \ + (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | \ + SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \ + SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ + SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | \ + SNDRV_PCM_RATE_96000) + +#define IMX_SSI_BITS \ + (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ + SNDRV_PCM_FMTBIT_S24_LE) + +struct snd_soc_cpu_dai imx_ssi_pcm_dai[] = { +{ + .name = "imx-i2s-1-0", + .id = IMX_DAI_SSI0, + .type = SND_SOC_DAI_I2S, + .suspend = imx_ssi_suspend, + .resume = imx_ssi_resume, + .playback = { + .channels_min = 1, + .channels_max = 2, + .formats = IMX_SSI_BITS, + .rates = IMX_SSI_RATES,}, + .capture = { + .channels_min = 1, + .channels_max = 2, + .formats = IMX_SSI_BITS, + .rates = IMX_SSI_RATES,}, + .ops = { + .startup = imx_ssi_startup, + .shutdown = imx_ssi_shutdown, + .trigger = imx_ssi_trigger, + .prepare = imx_ssi_prepare, + .hw_params = imx_ssi_hw_params,}, + .dai_ops = { + .set_sysclk = imx_ssi_set_dai_sysclk, + .set_clkdiv = imx_ssi_set_dai_clkdiv, + .set_fmt = imx_ssi_set_dai_fmt, + .set_tdm_slot = imx_ssi_set_dai_tdm_slot, + }, +}, +{ + .name = "imx-i2s-1-1", + .id = IMX_DAI_SSI1, + .type = SND_SOC_DAI_I2S, + .playback = { + .channels_min = 1, + .channels_max = 2, + .formats = IMX_SSI_BITS, + .rates = IMX_SSI_RATES,}, + .capture = { + .channels_min = 1, + .channels_max = 2, + .formats = IMX_SSI_BITS, + .rates = IMX_SSI_RATES,}, + .ops = { + .startup = imx_ssi_startup, + .shutdown = imx_ssi_shutdown, + .trigger = imx_ssi_trigger, + .prepare = imx_ssi_prepare, + .hw_params = imx_ssi_hw_params,}, +}, +{ + .name = "imx-i2s-2-0", + .id = IMX_DAI_SSI2, + .type = SND_SOC_DAI_I2S, + .suspend = imx_ssi_suspend, + .resume = imx_ssi_resume, + .playback = { + .channels_min = 1, + .channels_max = 2, + .formats = IMX_SSI_BITS, + .rates = IMX_SSI_RATES,}, + .capture = { + .channels_min = 1, + .channels_max = 2, + .formats = IMX_SSI_BITS, + .rates = IMX_SSI_RATES,}, + .ops = { + .startup = imx_ssi_startup, + .shutdown = imx_ssi_shutdown, + .prepare = imx_ssi_prepare, + .trigger = imx_ssi_trigger, + .hw_params = imx_ssi_hw_params,}, + .dai_ops = { + .set_sysclk = imx_ssi_set_dai_sysclk, + .set_clkdiv = imx_ssi_set_dai_clkdiv, + .set_fmt = imx_ssi_set_dai_fmt, + .set_tdm_slot = imx_ssi_set_dai_tdm_slot, + }, +}, +{ + .name = "imx-i2s-2-0", + .id = IMX_DAI_SSI3, + .type = SND_SOC_DAI_I2S, + .playback = { + .channels_min = 1, + .channels_max = 2, + .formats = IMX_SSI_BITS, + .rates = IMX_SSI_RATES,}, + .capture = { + .channels_min = 1, + .channels_max = 2, + .formats = IMX_SSI_BITS, + .rates = IMX_SSI_RATES,}, + .ops = { + .startup = imx_ssi_startup, + .shutdown = imx_ssi_shutdown, + .prepare = imx_ssi_prepare, + .trigger = imx_ssi_trigger, + .hw_params = imx_ssi_hw_params,}, +}, +}; +EXPORT_SYMBOL_GPL(imx_ssi_pcm_dai); + +/* Module information */ +MODULE_AUTHOR("Liam Girdwood, liam.girdwood@wolfsonmicro.com, www.wolfsonmicro.com"); +MODULE_DESCRIPTION("i.MX ASoC I2S driver"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/imx/imx-ssi.h b/sound/soc/imx/imx-ssi.h new file mode 100644 index 0000000..be761f3 --- /dev/null +++ b/sound/soc/imx/imx-ssi.h @@ -0,0 +1,215 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _IMX_SSI_H +#define _IMX_SSI_H + +#include + +/* SSI regs definition - MOVE to asm/arch when stable */ +#define SSI1_IO_BASE_ADDR IO_ADDRESS(SSI1_BASE_ADDR) +#define SSI2_IO_BASE_ADDR IO_ADDRESS(SSI2_BASE_ADDR) + +#define SSI1_STX0 *((volatile u32 *)(SSI1_IO_BASE_ADDR + 0x00)) +#define SSI1_STX1 *((volatile u32 *)(SSI1_IO_BASE_ADDR + 0x04)) +#define SSI1_SRX0 *((volatile u32 *)(SSI1_IO_BASE_ADDR + 0x08)) +#define SSI1_SRX1 *((volatile u32 *)(SSI1_IO_BASE_ADDR + 0x0c)) +#define SSI1_SCR *((volatile u32 *)(SSI1_IO_BASE_ADDR + 0x10)) +#define SSI1_SISR *((volatile u32 *)(SSI1_IO_BASE_ADDR + 0x14)) +#define SSI1_SIER *((volatile u32 *)(SSI1_IO_BASE_ADDR + 0x18)) +#define SSI1_STCR *((volatile u32 *)(SSI1_IO_BASE_ADDR + 0x1c)) +#define SSI1_SRCR *((volatile u32 *)(SSI1_IO_BASE_ADDR + 0x20)) +#define SSI1_STCCR *((volatile u32 *)(SSI1_IO_BASE_ADDR + 0x24)) +#define SSI1_SRCCR *((volatile u32 *)(SSI1_IO_BASE_ADDR + 0x28)) +#define SSI1_SFCSR *((volatile u32 *)(SSI1_IO_BASE_ADDR + 0x2c)) +#define SSI1_STR *((volatile u32 *)(SSI1_IO_BASE_ADDR + 0x30)) +#define SSI1_SOR *((volatile u32 *)(SSI1_IO_BASE_ADDR + 0x34)) +#define SSI1_SACNT *((volatile u32 *)(SSI1_IO_BASE_ADDR + 0x38)) +#define SSI1_SACADD *((volatile u32 *)(SSI1_IO_BASE_ADDR + 0x3c)) +#define SSI1_SACDAT *((volatile u32 *)(SSI1_IO_BASE_ADDR + 0x40)) +#define SSI1_SATAG *((volatile u32 *)(SSI1_IO_BASE_ADDR + 0x44)) +#define SSI1_STMSK *((volatile u32 *)(SSI1_IO_BASE_ADDR + 0x48)) +#define SSI1_SRMSK *((volatile u32 *)(SSI1_IO_BASE_ADDR + 0x4c)) + +#define SSI2_STX0 *((volatile u32 *)(SSI2_IO_BASE_ADDR + 0x00)) +#define SSI2_STX1 *((volatile u32 *)(SSI2_IO_BASE_ADDR + 0x04)) +#define SSI2_SRX0 *((volatile u32 *)(SSI2_IO_BASE_ADDR + 0x08)) +#define SSI2_SRX1 *((volatile u32 *)(SSI2_IO_BASE_ADDR + 0x0c)) +#define SSI2_SCR *((volatile u32 *)(SSI2_IO_BASE_ADDR + 0x10)) +#define SSI2_SISR *((volatile u32 *)(SSI2_IO_BASE_ADDR + 0x14)) +#define SSI2_SIER *((volatile u32 *)(SSI2_IO_BASE_ADDR + 0x18)) +#define SSI2_STCR *((volatile u32 *)(SSI2_IO_BASE_ADDR + 0x1c)) +#define SSI2_SRCR *((volatile u32 *)(SSI2_IO_BASE_ADDR + 0x20)) +#define SSI2_STCCR *((volatile u32 *)(SSI2_IO_BASE_ADDR + 0x24)) +#define SSI2_SRCCR *((volatile u32 *)(SSI2_IO_BASE_ADDR + 0x28)) +#define SSI2_SFCSR *((volatile u32 *)(SSI2_IO_BASE_ADDR + 0x2c)) +#define SSI2_STR *((volatile u32 *)(SSI2_IO_BASE_ADDR + 0x30)) +#define SSI2_SOR *((volatile u32 *)(SSI2_IO_BASE_ADDR + 0x34)) +#define SSI2_SACNT *((volatile u32 *)(SSI2_IO_BASE_ADDR + 0x38)) +#define SSI2_SACADD *((volatile u32 *)(SSI2_IO_BASE_ADDR + 0x3c)) +#define SSI2_SACDAT *((volatile u32 *)(SSI2_IO_BASE_ADDR + 0x40)) +#define SSI2_SATAG *((volatile u32 *)(SSI2_IO_BASE_ADDR + 0x44)) +#define SSI2_STMSK *((volatile u32 *)(SSI2_IO_BASE_ADDR + 0x48)) +#define SSI2_SRMSK *((volatile u32 *)(SSI2_IO_BASE_ADDR + 0x4c)) + +#define SSI_SCR_CLK_IST (1 << 9) +#define SSI_SCR_TCH_EN (1 << 8) +#define SSI_SCR_SYS_CLK_EN (1 << 7) +#define SSI_SCR_I2S_MODE_NORM (0 << 5) +#define SSI_SCR_I2S_MODE_MSTR (1 << 5) +#define SSI_SCR_I2S_MODE_SLAVE (2 << 5) +#define SSI_SCR_SYN (1 << 4) +#define SSI_SCR_NET (1 << 3) +#define SSI_SCR_RE (1 << 2) +#define SSI_SCR_TE (1 << 1) +#define SSI_SCR_SSIEN (1 << 0) + +#define SSI_SISR_CMDAU (1 << 18) +#define SSI_SISR_CMDDU (1 << 17) +#define SSI_SISR_RXT (1 << 16) +#define SSI_SISR_RDR1 (1 << 15) +#define SSI_SISR_RDR0 (1 << 14) +#define SSI_SISR_TDE1 (1 << 13) +#define SSI_SISR_TDE0 (1 << 12) +#define SSI_SISR_ROE1 (1 << 11) +#define SSI_SISR_ROE0 (1 << 10) +#define SSI_SISR_TUE1 (1 << 9) +#define SSI_SISR_TUE0 (1 << 8) +#define SSI_SISR_TFS (1 << 7) +#define SSI_SISR_RFS (1 << 6) +#define SSI_SISR_TLS (1 << 5) +#define SSI_SISR_RLS (1 << 4) +#define SSI_SISR_RFF1 (1 << 3) +#define SSI_SISR_RFF0 (1 << 2) +#define SSI_SISR_TFE1 (1 << 1) +#define SSI_SISR_TFE0 (1 << 0) + +#define SSI_SIER_RDMAE (1 << 22) +#define SSI_SIER_RIE (1 << 21) +#define SSI_SIER_TDMAE (1 << 20) +#define SSI_SIER_TIE (1 << 19) +#define SSI_SIER_CMDAU_EN (1 << 18) +#define SSI_SIER_CMDDU_EN (1 << 17) +#define SSI_SIER_RXT_EN (1 << 16) +#define SSI_SIER_RDR1_EN (1 << 15) +#define SSI_SIER_RDR0_EN (1 << 14) +#define SSI_SIER_TDE1_EN (1 << 13) +#define SSI_SIER_TDE0_EN (1 << 12) +#define SSI_SIER_ROE1_EN (1 << 11) +#define SSI_SIER_ROE0_EN (1 << 10) +#define SSI_SIER_TUE1_EN (1 << 9) +#define SSI_SIER_TUE0_EN (1 << 8) +#define SSI_SIER_TFS_EN (1 << 7) +#define SSI_SIER_RFS_EN (1 << 6) +#define SSI_SIER_TLS_EN (1 << 5) +#define SSI_SIER_RLS_EN (1 << 4) +#define SSI_SIER_RFF1_EN (1 << 3) +#define SSI_SIER_RFF0_EN (1 << 2) +#define SSI_SIER_TFE1_EN (1 << 1) +#define SSI_SIER_TFE0_EN (1 << 0) + +#define SSI_STCR_TXBIT0 (1 << 9) +#define SSI_STCR_TFEN1 (1 << 8) +#define SSI_STCR_TFEN0 (1 << 7) +#define SSI_STCR_TFDIR (1 << 6) +#define SSI_STCR_TXDIR (1 << 5) +#define SSI_STCR_TSHFD (1 << 4) +#define SSI_STCR_TSCKP (1 << 3) +#define SSI_STCR_TFSI (1 << 2) +#define SSI_STCR_TFSL (1 << 1) +#define SSI_STCR_TEFS (1 << 0) + +#define SSI_SRCR_RXBIT0 (1 << 9) +#define SSI_SRCR_RFEN1 (1 << 8) +#define SSI_SRCR_RFEN0 (1 << 7) +#define SSI_SRCR_RFDIR (1 << 6) +#define SSI_SRCR_RXDIR (1 << 5) +#define SSI_SRCR_RSHFD (1 << 4) +#define SSI_SRCR_RSCKP (1 << 3) +#define SSI_SRCR_RFSI (1 << 2) +#define SSI_SRCR_RFSL (1 << 1) +#define SSI_SRCR_REFS (1 << 0) + +#define SSI_STCCR_DIV2 (1 << 18) +#define SSI_STCCR_PSR (1 << 15) +#define SSI_STCCR_WL(x) ((((x) - 2) >> 1) << 13) +#define SSI_STCCR_DC(x) (((x) & 0x1f) << 8) +#define SSI_STCCR_PM(x) (((x) & 0xff) << 0) +#define SSI_STCCR_WL_MASK (0xf << 13) +#define SSI_STCCR_DC_MASK (0x1f << 8) +#define SSI_STCCR_PM_MASK (0xff << 0) + +#define SSI_SRCCR_DIV2 (1 << 18) +#define SSI_SRCCR_PSR (1 << 15) +#define SSI_SRCCR_WL(x) ((((x) - 2) >> 1) << 13) +#define SSI_SRCCR_DC(x) (((x) & 0x1f) << 8) +#define SSI_SRCCR_PM(x) (((x) & 0xff) << 0) +#define SSI_SRCCR_WL_MASK (0xf << 13) +#define SSI_SRCCR_DC_MASK (0x1f << 8) +#define SSI_SRCCR_PM_MASK (0xff << 0) + + +#define SSI_SFCSR_RFCNT1(x) (((x) & 0xf) << 28) +#define SSI_SFCSR_TFCNT1(x) (((x) & 0xf) << 24) +#define SSI_SFCSR_RFWM1(x) (((x) & 0xf) << 20) +#define SSI_SFCSR_TFWM1(x) (((x) & 0xf) << 16) +#define SSI_SFCSR_RFCNT0(x) (((x) & 0xf) << 12) +#define SSI_SFCSR_TFCNT0(x) (((x) & 0xf) << 8) +#define SSI_SFCSR_RFWM0(x) (((x) & 0xf) << 4) +#define SSI_SFCSR_TFWM0(x) (((x) & 0xf) << 0) + +#define SSI_STR_TEST (1 << 15) +#define SSI_STR_RCK2TCK (1 << 14) +#define SSI_STR_RFS2TFS (1 << 13) +#define SSI_STR_RXSTATE(x) (((x) & 0xf) << 8) +#define SSI_STR_TXD2RXD (1 << 7) +#define SSI_STR_TCK2RCK (1 << 6) +#define SSI_STR_TFS2RFS (1 << 5) +#define SSI_STR_TXSTATE(x) (((x) & 0xf) << 0) + +#define SSI_SOR_CLKOFF (1 << 6) +#define SSI_SOR_RX_CLR (1 << 5) +#define SSI_SOR_TX_CLR (1 << 4) +#define SSI_SOR_INIT (1 << 3) +#define SSI_SOR_WAIT(x) (((x) & 0x3) << 1) +#define SSI_SOR_SYNRST (1 << 0) + +#define SSI_SACNT_FRDIV(x) (((x) & 0x3f) << 5) +#define SSI_SACNT_WR (x << 4) +#define SSI_SACNT_RD (x << 3) +#define SSI_SACNT_TIF (x << 2) +#define SSI_SACNT_FV (x << 1) +#define SSI_SACNT_AC97EN (x << 0) + +/* SDMA watermarks for FIFO's */ +#define SDMA_TXFIFO_WATERMARK 0x4 +#define SDMA_RXFIFO_WATERMARK 0x6 + +/* i.MX DAI SSP ID's */ +#define IMX_DAI_SSI0 0 /* SSI1 FIFO 0 */ +#define IMX_DAI_SSI1 1 /* SSI1 FIFO 1 */ +#define IMX_DAI_SSI2 2 /* SSI2 FIFO 0 */ +#define IMX_DAI_SSI3 3 /* SSI2 FIFO 1 */ + +/* SSI clock sources */ +#define IMX_SSP_SYS_CLK 0 + +/* SSI audio dividers */ +#define IMX_SSI_TX_DIV_2 0 +#define IMX_SSI_TX_DIV_PSR 1 +#define IMX_SSI_TX_DIV_PM 2 +#define IMX_SSI_RX_DIV_2 3 +#define IMX_SSI_RX_DIV_PSR 4 +#define IMX_SSI_RX_DIV_PM 5 + + +/* SSI Div 2 */ +#define IMX_SSI_DIV_2_OFF ~SSI_STCCR_DIV2 +#define IMX_SSI_DIV_2_ON SSI_STCCR_DIV2 + +extern struct snd_soc_cpu_dai imx_ssi_pcm_dai[4]; + +#endif diff --git a/sound/soc/imx/imx21-pcm.c b/sound/soc/imx/imx21-pcm.c new file mode 100644 index 0000000..de6de85 --- /dev/null +++ b/sound/soc/imx/imx21-pcm.c @@ -0,0 +1,454 @@ +/* + * linux/sound/arm/mxc-pcm.c -- ALSA SoC interface for the Freescale i.MX CPU's + * + * Copyright 2006 Wolfson Microelectronics PLC. + * Author: Liam Girdwood + * liam.girdwood@wolfsonmicro.com or linux@wolfsonmicro.com + * + * Based on pxa2xx-pcm.c by Nicolas Pitre, (C) 2004 MontaVista Software, Inc. + * and on mxc-alsa-mc13783 (C) 2006 Freescale. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Revision history + * 29th Aug 2006 Initial version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "imx-pcm.h" + +/* debug */ +#define IMX_DEBUG 0 +#if IMX_DEBUG +#define dbg(format, arg...) printk(format, ## arg) +#else +#define dbg(format, arg...) +#endif + +static const struct snd_pcm_hardware mxc_pcm_hardware = { + .info = (SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_BLOCK_TRANSFER | + SNDRV_PCM_INFO_MMAP | + SNDRV_PCM_INFO_MMAP_VALID | + SNDRV_PCM_INFO_PAUSE | + SNDRV_PCM_INFO_RESUME), + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE, + .buffer_bytes_max = 32 * 1024, + .period_bytes_min = 64, + .period_bytes_max = 8 * 1024, + .periods_min = 2, + .periods_max = 255, + .fifo_size = 0, +}; + +struct mxc_runtime_data { + int dma_ch; + struct mxc_pcm_dma_param *dma_params; +}; + +/*! + * This function stops the current dma transfert for playback + * and clears the dma pointers. + * + * @param substream pointer to the structure of the current stream. + * + */ +static void audio_stop_dma(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct mxc_runtime_data *prtd = runtime->private_data; + unsigned int dma_size = frames_to_bytes(runtime, runtime->period_size); + unsigned int offset dma_size * s->periods; + unsigned long flags; + + spin_lock_irqsave(&prtd->dma_lock, flags); + + dbg("MXC : audio_stop_dma active = 0\n"); + prtd->active = 0; + prtd->period = 0; + prtd->periods = 0; + + /* this stops the dma channel and clears the buffer ptrs */ + mxc_dma_stop(prtd->dma_wchannel); + if(substream == SNDRV_PCM_STREAM_PLAYBACK) + dma_unmap_single(NULL, runtime->dma_addr + offset, dma_size, + DMA_TO_DEVICE); + else + dma_unmap_single(NULL, runtime->dma_addr + offset, dma_size, + DMA_FROM_DEVICE); + + spin_unlock_irqrestore(&prtd->dma_lock, flags); +} + +/*! + * This function is called whenever a new audio block needs to be + * transferred to mc13783. The function receives the address and the size + * of the new block and start a new DMA transfer. + * + * @param substream pointer to the structure of the current stream. + * + */ +static int dma_new_period(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct mxc_runtime_data *prtd = runtime->private_data; + unsigned int dma_size; + unsigned int offset; + int ret=0; + dma_request_t sdma_request; + + if (prtd->active){ + memset(&sdma_request, 0, sizeof(dma_request_t)); + dma_size = frames_to_bytes(runtime, runtime->period_size); + dbg("s->period (%x) runtime->periods (%d)\n", + s->period,runtime->periods); + dbg("runtime->period_size (%d) dma_size (%d)\n", + (unsigned int)runtime->period_size, + runtime->dma_bytes); + + offset = dma_size * prtd->period; + snd_assert(dma_size <= DMA_BUF_SIZE, ); + if(substream == SNDRV_PCM_STREAM_PLAYBACK) + sdma_request.sourceAddr = (char*)(dma_map_single(NULL, + runtime->dma_area + offset, dma_size, DMA_TO_DEVICE)); + else + sdma_request.destAddr = (char*)(dma_map_single(NULL, + runtime->dma_area + offset, dma_size, DMA_FROM_DEVICE)); + sdma_request.count = dma_size; + + dbg("MXC: Start DMA offset (%d) size (%d)\n", offset, + runtime->dma_bytes); + + mxc_dma_set_config(prtd->dma_wchannel, &sdma_request, 0); + if((ret = mxc_dma_start(prtd->dma_wchannel)) < 0) { + dbg("audio_process_dma: cannot queue DMA buffer\ + (%i)\n", ret); + return err; + } + prtd->tx_spin = 1; /* FGA little trick to retrieve DMA pos */ + prtd->period++; + prtd->period %= runtime->periods; + } + return ret; +} + + +/*! + * This is a callback which will be called + * when a TX transfer finishes. The call occurs + * in interrupt context. + * + * @param dat pointer to the structure of the current stream. + * + */ +static void audio_dma_irq(void *data) +{ + struct snd_pcm_substream *substream; + struct snd_pcm_runtime *runtime; + struct mxc_runtime_data *prtd; + unsigned int dma_size; + unsigned int previous_period; + unsigned int offset; + + substream = data; + runtime = substream->runtime; + prtd = runtime->private_data; + previous_period = prtd->periods; + dma_size = frames_to_bytes(runtime, runtime->period_size); + offset = dma_size * previous_period; + + prtd->tx_spin = 0; + prtd->periods++; + prtd->periods %= runtime->periods; + + /* + * Give back to the CPU the access to the non cached memory + */ + if(substream == SNDRV_PCM_STREAM_PLAYBACK) + dma_unmap_single(NULL, runtime->dma_addr + offset, dma_size, + DMA_TO_DEVICE); + else + dma_unmap_single(NULL, runtime->dma_addr + offset, dma_size, + DMA_FROM_DEVICE); + /* + * If we are getting a callback for an active stream then we inform + * the PCM middle layer we've finished a period + */ + if (prtd->active) + snd_pcm_period_elapsed(substream); + + /* + * Trig next DMA transfer + */ + dma_new_period(substream); +} + +/*! + * This function configures the hardware to allow audio + * playback operations. It is called by ALSA framework. + * + * @param substream pointer to the structure of the current stream. + * + * @return 0 on success, -1 otherwise. + */ +static int +snd_mxc_prepare(struct snd_pcm_substream *substream) +{ + struct mxc_runtime_data *prtd = runtime->private_data; + struct snd_soc_pcm_runtime *rtd = substream->private_data; + int ret = 0; + prtd->period = 0; + prtd->periods = 0; + + dma_channel_params params; + int channel = 0; // passed in ? + + if ((ret = mxc_request_dma(&channel, "ALSA TX SDMA") < 0)){ + dbg("error requesting a write dma channel\n"); + return ret; + } + + /* configure DMA params */ + memset(¶ms, 0, sizeof(dma_channel_params)); + params.bd_number = 1; + params.arg = s; + params.callback = callback; + params.transfer_type = emi_2_per; + params.watermark_level = SDMA_TXFIFO_WATERMARK; + params.word_size = TRANSFER_16BIT; + //dbg(KERN_ERR "activating connection SSI1 - SDMA\n"); + params.per_address = SSI1_BASE_ADDR; + params.event_id = DMA_REQ_SSI1_TX1; + params.peripheral_type = SSI; + + /* set up chn with params */ + mxc_dma_setup_channel(channel, ¶ms); + s->dma_wchannel = channel; + + return ret; +} + +static int mxc_pcm_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + int ret; + + if((ret=snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0) + return ret; + runtime->dma_addr = virt_to_phys(runtime->dma_area); + + return ret; +} + +static int mxc_pcm_hw_free(struct snd_pcm_substream *substream) +{ + return snd_pcm_lib_free_pages(substream); +} + +static int mxc_pcm_trigger(struct snd_pcm_substream *substream, int cmd) +{ + struct mxc_runtime_data *prtd = substream->runtime->private_data; + int ret = 0; + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + prtd->tx_spin = 0; + /* requested stream startup */ + prtd->active = 1; + ret = dma_new_period(substream); + break; + case SNDRV_PCM_TRIGGER_STOP: + /* requested stream shutdown */ + ret = audio_stop_dma(substream); + break; + case SNDRV_PCM_TRIGGER_SUSPEND: + prtd->active = 0; + prtd->periods = 0; + break; + case SNDRV_PCM_TRIGGER_RESUME: + prtd->active = 1; + prtd->tx_spin = 0; + ret = dma_new_period(substream); + break; + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + prtd->active = 0; + break; + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + prtd->active = 1; + if (prtd->old_offset) { + prtd->tx_spin = 0; + ret = dma_new_period(substream); + } + break; + default: + ret = -EINVAL; + break; + } + + return ret; +} + +static snd_pcm_uframes_t mxc_pcm_pointer(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct mxc_runtime_data *prtd = runtime->private_data; + unsigned int offset = 0; + + /* tx_spin value is used here to check if a transfert is active */ + if (prtd->tx_spin){ + offset = (runtime->period_size * (prtd->periods)) + + (runtime->period_size >> 1); + if (offset >= runtime->buffer_size) + offset = runtime->period_size >> 1; + } else { + offset = (runtime->period_size * (s->periods)); + if (offset >= runtime->buffer_size) + offset = 0; + } + + return offset; +} + + +static int mxc_pcm_open(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct mxc_runtime_data *prtd; + int ret; + + snd_soc_set_runtime_hwparams(substream, &mxc_pcm_hardware); + + if ((err = snd_pcm_hw_constraint_integer(runtime, + SNDRV_PCM_HW_PARAM_PERIODS)) < 0) + return err; + if ((err = snd_pcm_hw_constraint_list(runtime, 0, + SNDRV_PCM_HW_PARAM_RATE, &hw_playback_rates)) < 0) + return err; + msleep(10); // liam - why + + /* setup DMA controller for playback */ + if((err = configure_write_channel(&mxc_mc13783->s[SNDRV_PCM_STREAM_PLAYBACK], + audio_dma_irq)) < 0 ) + return err; + + if((prtd = kzalloc(sizeof(struct mxc_runtime_data), GFP_KERNEL)) == NULL) { + ret = -ENOMEM; + goto out; + } +